High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure

• US 4,851,990 A
• Filed: 02/09/1987
• Issued: 07/25/1989
• Est. Priority Date: 02/09/1987
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Johnson, William M., Baror, Gigy
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Lee, Thomas C.
• Application Number:
  US07/012,226
• Time in Patent Office: 897 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/100
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 15/7835 on more than one IC chip

Abstract

Methods and apparatus for realizing a high performance interface between a processor, constituting part of a reduced instruction set computer (RISC) system, and a set of devices, including memory means. According to the invention, the interface includes three independent buses. A shared processor output bus, a processor input instruction bus, and a bidirectional data bus. The shared processor output address bus coupled the processor and the computer'"'"'s memory. This bus carries both instructon and data access signals being transmitted by the processor to the memory. The processor input instruction bus also couples the processor and the computer'"'"'s memory means, but carries instruction signals being transmitted from the memory to the processor. The bidirectional data bus provides a signal path for carrying data signals being transmitted by the memory to the processor and vice-a-versa. The novel interface uses demultiplexed buses for simpler timing and uses the separate data and instruction buses to provide extremely high transfer rates at a reasonable cost. The shared address bus accommodates pipelined and burst mode processor protocols with the burst mode protocol allowing concurrent data and instruction transfers. Methods and apparatus for controlling the buses and reporting bus status, etc., are also part of the invention and facilitate the implementation of features that include status reporting, handshaking between devices and the RISC processor, and bus arbitration.

Claims

1. A high performance interface between a single chip processor, constituting part of a reduced instruction set computer (RISC) system, and a set of off chip devices, including memory means, said processor having a plurality of different off chip memory access protocols, wherein said interface comprises:

(a) a shared processor output address bus, coupling said processor and said off chip memory means, for carrying both instruction and data access signals being transmitted by said processor to said off chip memory means;

(b) a dedicated processor input instruction bus, coupling said processor and said off chip memory means, for carrying only instruction signals being transmitted by said off chip memory means to said processor; and

(c) a bidirectional data bus coupling said processor and said off chip memory means, for carrying data signals being transmitted by said off chip memory means to said processor and for carrying data signals being transmitted by said processor to said off chip memory means, which in at least one of said protocols operates simultaneously with said dedicated processor instruction bus.

2. An interface as set forth in claim 1 further comprising a plurality of signal paths used for carrying signals belonging to a set of processor and device generated signals which are used to control said buses.

3. An interface as set forth in claim 2 wherein said buses are synchronous, independent signal paths.

4. An interface as set forth in claim 2 wherein said buses, said signal paths and said set of signals support the performance of a simple memory access protocol by said processor.

5. An interface as set forth in claim 2 wherein said buses, said signal paths and said set of signals support the performance of a pipelined memory access protocol by said processor.

6. An interface as set forth in claim 5 in which both pipelined instruction accesses and pipelined data accesses may be performed by said processor over said address bus.

7. An interface as set forth in claim 2 wherein said buses, said signal paths and said set of signals support the performance of a burst mode access protocol by said processor.

8. An interface as set forth in claim 2 wherein said buses, said signal paths and said set of signals support the performance of simple memory access, pipelined memory access and burst mode memory access protocols by said processor.

9. An interface as set forth in claim 2 over which data accesses and data transfers may be performed during the same clock cycle as instruction accesses and instruction transfers.

10. An interface as set forth in claim 2 wherein said address bus, said instruction bus and said data bus are each 32 bits wide.

11. An interface as set forth in claim 10 in which each of said buses is interconnected to said processor via a 32 pin signal interface forming a part of the integrated circuit package containing said processor.

12. An interface as set forth in claim 1 wherein said plurality of signal paths are each interconnected to said processor via a separate pin signal interface forming a part of the integrated circuit package containing said processor.

13. An interface as set forth in claim 2 wherein said buses are demultiplexed.

14. An interface as set forth in claim 2 over which instruction accesses by said processor may be selectively made to an instruction memory space and an instruction read only memory space( where both of said spaces are included in said off chip memory means.

15. An interface as set forth in claim 14 wherein said memory space selection by said processor is signalled to said off chip memory means over one of said plurality of signal paths via the state of an instruction request signal included in said set of processor generated signals.

16. An interface as set forth in claim 2 over which data accesses by said processor may be selectively made to a data memory space, an input/output space and a coprocessor space, where all of said spaces are included in said off chip memory means.

17. An interface as set forth in claim 16 wherein said memory space, selected by said processor is signalled to said off chip memory means over two of said plurality of signal paths via the state of a two bit data request signal.

18. A high performance interface between a single chip processor, constituting part of a reduced instruction set computer (RISC) system, and a set of off chip devices, including off chip memory means, said processor having a plurality of different off chip memory access protocols, wherein said interface comprises:

(a) a shred processor output address bus, coupling said processor and said off chip memory means, for carrying both instruction and data access signals being transmitted by said processor to said off chip memory means;

(b) a dedicated processor input instruction bus, coupling said processor and said off chip memory means, for carrying only instruction signals being transmitted by said off chip memory means to said processor;

(c) a bidirectional data bus coupling said processor and said off chip memory means, for carrying data signals being transmitted by said off chip memory means to said processor and for carrying data signals being transmitted by said processor to said off chip memory means, which in at least one of said protocols operates simultaneously with said dedicated processor instruction bus; and

(d) a plurality of signal paths used for carrying signals belonging to a set of processor and off chip device generated signals which are used to control said buses.

19. An interface as set forth in claim 18 in which said set of signals include instruction address transfer and instruction address request signals.

20. An interface as set forth in claim 18 in which said set of signals include instruction transfer signals.

21. An interface as set forth in claim 18 in which said set of signals include data address transfer and data address request signals.

22. An interface as set forth in claim 18 in which said set of signals include data transfer signals.

23. An interface as set forth in claim 18 in which said set of signals include bus arbitration signals.

24. An interface as set forth in claim 18 in which said set of signals include bus status and test signals.

25. A method for achieving a high performance interface between a single chip processor constituting part of a reduced instruction set computer (RISC) system, and a set of off chip devices, including off chip memory means, said processor having a plurality of different off chip memory access protocols, comprising the steps of:

(a) transmitting instruction and data access signals from said processor to said off chip memory means utilizing a shared address bus;

(b) transmitting instructions from said off chip memory means to said processor via a dedicated instruction bus, independent of said shared address bus; and

(c) transmitting data between said processor and said off chip memory means via data bus which is independent of both said dedicated instruction bus and said address bus and which in at least one of said protocols operates simultaneously with said dedicated processor instruction bus.

27. A method as set forth in claim 25 wherein said steps of transmitting are all performed synchronously.

32. A method as set forth in claim 25 in which the steps of transmitting said data access signals and said data may be performed during the same clock cycle as the steps of transmitting of said instruction access signals and said instructions.

33. A method as set forth in claim 25 in which said step of transmitting instruction access and data access signals further includes the step of signalling which of a plurality of instruction spaces is being accessed by said processor.

34. A method as set forth in claim 25 in which said step of transmitting instructions and data access signals further includes the step of signalling which of a plurality of data spaces is being accessed by said processor.

26. A method as set forth in claim 26 further comprising the step of transmitting over a plurality of signal paths, signals belonging to a set of processor and off chip device generated signals which are used to control said buses.

28. A method as set forth in claim 26 further comprising the step of performing a simple memory access protocol utilizing the combination of said processor, said off chip memory means, said buses, said set of signals and said signal paths.

29. A method as set forth in claim 26 further comprising the step of performing a pipelined memory access protocol utilizing the combination of said processor, said off chip memory means, said buses, said set of signals and said signal paths.

30. A method as set forth in claim 29 wherein said step of performing a pipelined memory access protocol includes the performance of pipelined instruction accesses and pipelined data accesses over said shared address bus.

31. A method as set forth in claim 26 further comprising the step of performing a burst mode access protocol utilizing the combination of said processor, said off chip memory means, said buses, said set of signals and said signal paths.