Polynomial operator in galois fields and a digital signal processor comprising an operator of this type

• US 4,852,098 A
• Filed: 10/22/1987
• Issued: 07/25/1989
• Est. Priority Date: 10/22/1986
• Status: Expired due to Fees

• Current Assignee: Thomson-CSF
• Original Assignee: Thomson-CSF
• Inventors: Laurent, Pierre-Andre, Brechard, Dominique
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US07/111,280
• Time in Patent Office: 642 Days
• Field of Search: 371/37, 371/38, 371/39, 371/40
• US Class Current: 714/782
• CPC Class Codes: G06F 7/724 Finite field arithmetic for error detection or correction in general H03M13/00, in computers G06F11/10
• CPC Class Codes: H03M 13/033 Theoretical methods to calculate these checking codes

Abstract

The polynomial operator in the Galois field of the invention is organized at three levels:

a multiplexer level to select and transmit the operands to be used for the successive stage of the calculation to a second level;

a so-called pipeline level comprising 3 flip-flop registers to memorize the operands selected at the first level;

a third level for calculation, comprising a multiplier-adder which has its inputs X, Y and Z connected to the outputs of the registers, and which gives the coefficients of the resultant polynomials in the Galois field while always performing the same calculation by repetition of the same control instruction. This operator can be applied to digital telecommunications for the encoding and decoding of BCH or RS (REED SOLOMON) error-correcting codes, and can be used to make an integrated processor capable of processing digital data in the form of octets.

Claims

1. A polynomial operator in Galois fields organized at three successive levels:

a first level for the selection of operands comprising a multiplexing circuit, with three Balois value outputs;

a so-called "pipeline" level, comprising three memory registers having three multiple inputs connected to the outputs of the multiplexing circuit, to memorize three operands, along with three associated outputs;

and a calculating level comprising a multiplier/adder circuit in said Galois fields, the said circuit comprising two multiplier inputs, connected to the outputs of two of the memory registers, one adder input, connected to the output of the third memory register, the multiplier/adder circuit always performing the calculation X+(Y×

Z) where + and ×

represent addition and multiplication in said Galois fields, said multiplier/adder circuit outputting a result output;

and wherein the inputs of the multiplexing circuit are inputs of operands to receive Galois values from outside the operator, with, in addition, at least one input connected to the output of one of the memory registers, and one input connected to the result output of the multiplier/adder, the selection of one of the three inputs of the multiplexing circuit being programmed so that the calculating instruction X+(Y×

Z) is unchanged regardless of the type of polynomial operation to be performed in a particular Galois field.

2. An operator according to claim 1, wherein:

the multiplexing circuit has two inputs of operands, the first register being always fed by the same operand input, a second register being fed by either of the operand inputs or by the result output via a multiplexer, the third register being fed by an operand input through the result output or through the output of the second register.

3. An operator according to claim 1, wherein:

since each operand Galois value at the input of the operator is allocated an additional validity bit, the operator further comprises a processing circuit for validity bits, having one-bit memories associated with each of the validity bits of the input operands, control inputs and an output giving the validity bit to be assigned to the result output of the multiplier-adder to form the result output available at the output of the operator.

4. An operator according to claim 1, wherein:

in processing Galois values in one of the five Galois fields with 16, 32, 64, 128 or 256 elements, respectively comprising elements with 4, 5, 6, 7 or 8 significant bits, the multiplier-adder circuit has 5 circuits for the division of the result obtained from a maximum of 15 bits, respectively by the generator polynomials of these field to carry the results to the equivalent Galois values having a maximum of 8 bits.

5. An operator according to claim 1, wherein:

a resultant integrated structure having at least 9 active layers as made by VLSI technology.

6. An operator according to claim 1 wherein:

a digital signal processor capable of being parameterized encodes and/or decodes BCH and REED SOLOMON error correcting and detecting codes.