Process for manufacture of a vertical DMOS transistor

• US 4,853,345 A
• Filed: 08/22/1988
• Issued: 08/01/1989
• Est. Priority Date: 08/22/1988
• Status: Expired due to Term

• Current Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Original Assignee: Delco Electronics Corporation (Motors Liquidation Co. GUC Trust)
• Inventors: Himelick, James M.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US07/234,761
• Time in Patent Office: 344 Days
• Field of Search: 437/41, 437/915, 437/152, 437/187, 437/203, 437/228, 437/147, 437/153, 357/23.4
• US Class Current: 438/274
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A process for forming a vertical n-channel DMOS transistor uses a common deposition step to form a phosphorus-rich predeposit simultaneously over the polysilicon gate electrode, over a central surface portion of a p-well region and over the back surface drain region of the chip. This predeposit is followed by a common drive-in step to form an n-type source region within the p-well region, and to make the polysilicon gate electrode and the back surface more conductive. In addition, the process uses the source region contact mask as a shadow mask for anistropically etching a via hole in the source region so that the source metallization can also contact the p-well region and serve also as a shorting contact to the p-well.

Claims

1. A process for making a semiconductive device comprising the steps of:

preparing a silicon wafer of one conductivity type having opposed front and back surfaces;

forming over the front surface and insulated therefrom a patterned polysilicon layer suitable for use as a silicon gate electrode;

using the polysilicon layer as a mask for forming over the front surface a surface well having a conductivity type opposite said one type;

doping simultaneously with dopant ions of the type characteristic of the one-type a surface portion of said surface well, the polysilicon layer and the back surface of the water, which had been previously stripped of any polysilicon or oxide;

driving in said dopants to form a source region of the one conductivity type at the surface of the well region, leaving unconverted a channel portion and a body diode portion of the well region, and to increase the conductivity of the polysilicon layer and of the back surface; and

providing a source electrode contacting both the source region and the body diode portion and providing a drain electrode contacting the back surface.

2. The process of claim 1 in which the providing of the source electrode includes:

forming an insulating layer over the front surface and the patterned polysilicon layer;

providing a masking layer over said insulating layer;

forming an opening in said masking layer over a central portion of the source region;

etching isotropically the insulating layer through the opening in the masking layer to form an opening in the insulating layer that undercuts the masking layer and exposes a portion of the source region at such opening;

etching substantially anisotropically the exposed portion of the source region to form a via, through the source region to the underlying body diode portion of the well region, whose area essentially corresponds to that of the opening in the masking layer; and

depositing a conductive layer for use as the source electrode that contacts the source region along the side and top edges of the via and the body diode portion of the well region by way of the via.

3. A process for making a vertical DMOS transistor comprising the steps of:

preparing a silicon wafer of one conductivity type with front and back surfaces;

forming on the front surface a silicon oxide gate layer;

forming over said silicon oxide layer a patterned polysilicon layer suitable for use as a silicon gate electrode;

forming in a portion of the front surface of the wafer a surface well of the opposite conductivity type using the patterned polysilicon gate as a mask;

stripping the back surface of the wafer and the exposed surface of the well region of the gate oxide layer;

exposing the silicon wafer to an ambient of dopants of the conductivity type predominant in the wafer simultaneously to form a source region of the one conductivity type at the surface of the well region, to dope the polysilicon layer to adapt it for use as the gate electrode, and to open the back surface of the wafer to facilitate the provision thereto of a drain electrode; and

forming source and drain electrodes to the source region and the back surface of the bulk portion, respectively.

4. The process of claim 3 in which the forming of source electrode to the source region includes the steps of:

forming an insulating layer over the front surface;

forming over said insulating layer a masking layer defining an aperture overlying the source region;

etching the insulating layer isotropically through the aperture in the masking layer for forming an opening in the insulating layer larger than said aperture for exposing a portion of the source region;

etching substantially anisotropically the source region for forming a via to the underlying well region of area substantially corresponding to that of the aperture in the masking layer;

stripping away the masking layer; and

depositing a metal layer for use as the source electrode over said insulating layer for filling the opening in the insulating layer, thereby contacting the well region by way of the via in the source region and the source region along the vertical and lateral edges of the via.

5. In a process of making a DMOS transistor that comprises a source electrode that contacts both a central portion of a body diode portion of a well region of one conductivity type and an annular source region of the opposite conductivity type surrounding said central portion, the steps of:

forming, on a first surface of a semiconductive wafer whose bulk is of one conductivity type, a well region of the opposite conductivity type that surrounds an island surface region which is of the one conductivity type and is useful as a source region;

depositing an insulating layer over said first surface;

depositing a masking layer over said insulating layer;

forming an opening in the masking layer overlying a central portion of the island surface region;

etching the insulating layer through the opening in the masking layer in a manner to undercut the masking layer and form an opening in the insulating layer of an area larger than the opening in the masking layer;

etching the wafer through the openings in the masking and insulating layers to form a via through a central portion of said island surface region of an area substantially corresponding to the area of the opening in the masking layer, leaving exposed edge portions of the via;

stripping the masking layer; and

depositing a layer suitable for use as the source electrode over the insulating layer through the opening in the insulating layer and the via in the island surface region to contact both the island surface region at the exposed edges of the via and the underlying body diode portion of the well region through the via in the island surface region.

6. The process of claim 5 in which the etching of the insulating layer through the opening in the masking layer uses an isotropic wet etchant while the etching of the wafer to form a via uses a plasma etch that is substantially anisotropic.

7. The process of claim 6 which includes after the etching of the wafer and before the stripping of the masking layer the step of etching the insulating layer selectively to further expose the island surface region around the periphery of the via.