Process for manufacture of a semiconductor memory device

• US 4,853,348 A
• Filed: 12/22/1987
• Issued: 08/01/1989
• Est. Priority Date: 12/05/1984
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kimata, Masafumi, Tsubouchi, Natsuro
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US07/137,298
• Time in Patent Office: 588 Days
• Field of Search: 437/47, 437/60, 437/203, 437/228, 156/643, 156/644, 357/23.6
• US Class Current: 438/246
• CPC Class Codes: H01L 29/92 Capacitors having potential barriers
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate
• CPC Class Codes: Y10S 148/014 Capacitor
• CPC Class Codes: Y10S 438/901 Capacitive junction

Abstract

A semiconductor memory device such as a MOS dynamic RAM comprises transistor portions (2, 3 and 5) for writing and reading a signal and capacitor portions (1, 2, 6 and 9) by pn junction for storing a signal. The capacitor portions have preferably as large a capacitance as possible. For this purpose, a capacitor hole (7) is formed in a p type semiconductor substrate (6) and an n type semiconductor region (9) is provided along the capacitor hole (7) so that the pn junction area therebetween is increased and the capacitance is made large.

Claims

1. A method of manufacturing a semiconductor memory device having a capacitor, comprising the steps of:

(a) forming a substrate of a first conductive type;

(b) forming a capacitor hole in said substrate such that said capacitor hole includes a generally vertical passage extending within the substrate and which passage terminates in a cavity formed with a curved surface portion extending in the substrate;

(c) forming a semiconductor region of a second conductive type on said substrate and which semiconductor region extends coextensive with said passage and areas defining said cavity and such that a resulting generally vertical passage defined by the semiconductive region is dimensionally smaller in cross section than a corresponding cross section of the cavity formed within the substrate;

whereby a capacitor region is formed within said capacitor hole between said substrate of the first conductive type and said semiconductor region of the second conductive type.

2. The method of claim 1, wherein said capacitor hole is formed by isotropic etching.

3. The method of claim 1, wherein said capacitor hole is formed with a concave portion defining said curved surface portion.

4. The method of claim 1, wherein said capacitor hole is formed with curved surface regions extending within said substrate and which curved surface regions extend continuously between said vertical passage and a substantially flat bottom surface defining the bottom of the capacitor hole.

5. The method of claim 1, wherein said capacitor hole, in plan view, is of generally rectangular configuration.

6. A method of manufacturing a semiconductor memory device using a capacitor as a memory device, comprising the steps of:

(a) forming a substrate of a first conductive type;

(b) forming a generally vertical hole in the substrate extending substantially vertically to an upper surface thereof and forming an enlarged buried well within the substrate at a lower end of the generally vertical hole;

(c) forming a semiconductor region of a second conductive type in said substrate of the first conductive type with said semiconductor region extending generally along said generally vertical hole and along said enlarged buried well;

(d) said enlarged buried well establishing a capacitor region between said substrate of the first conductive type and said semiconductor region of the second conductive type, said buried well being formed by an isotropic etching process such that said well has a generally flat bottom surface and includes a curved surface region extending continuously between said bottom to the lower end of the generally vertically hole, said well being wider than the generally vertical hole.