Method for data reduction of digital image sequences

• US 4,853,779 A
• Filed: 04/07/1988
• Issued: 08/01/1989
• Est. Priority Date: 04/07/1987
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: von Brandt, Achim, Hammer, Bernard
• Primary Examiner(s): Britton, Howard W.
• Assistant Examiner(s): Kostak, Victor R.
• Application Number:
  US07/178,567
• Time in Patent Office: 481 Days
• Field of Search: 358/133, 358/135, 358/136
• US Class Current: 375/240.22
• CPC Class Codes: G06T 9/008 Vector quantisation
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/63 using sub-band based transform, e.g. wavelets
• CPC Class Codes: H04N 19/94 Vector quantisation

Abstract

A method for data reduction of digital image sequences in heirarchic fashion by means of a multi-stage coder on the basis of vector quantizing and movement compensation, as well as reconstruction of these image sequences by means of a multi-stage decoder. An input image signal is represented in a plurality of image signals having different spatial resolutions by means of a cascade of L identical low-pass filters having subsequent sub-scanning, whereby the spatial resolution and the data volume of the input image signal in the horizontal and the vertical directions are respectively reduced by a factor R in every cascade stage, and whereby the input signal is referenced "resolution level L" and the low-pass filter image signal having the smallest resolution is referenced "resolution level .0.". The chronologically preceding, reconstructed, movement-compensated image signal is represented in a plurality of image signals having different topical resolution in the same way. The samples of the resolution levels are subdivided into blocks, whereby the "resolution level .0." has the block size "1×1" and, for the next, the block size is horizontally and vertically increased by the factor R with every further resolution level but a block assumes the maximum block size N×N.

Claims

1. A method for data reduction of digital image sequences in hierarchic fashion by means of a multi-stage coder on the basis of vector quantizing and movement compensation as well as reconstruction of these image sequences by means of a multi-stage decoder, comprising the steps of

representing an input image signal in a plurality of image signals having different spatial resolution on the basis of a cascade of L identical quantizers having subsequent sub-scanning, whereby the spatial resolution and the data volume of the input image signal are respectively reduced by a factor R in the horizontal and in the vertical directions in every cascade stage and whereby the input image signal is referenced "resolution level L" and the low-pass-filtered image signal having the smallest resolution is referenced "resolution level 0";

representing the chronologically preceding, reconstructed, movement-compensated image signal by a plurality of image signals having different spatial resolution in the same way;

subdividing the samples of the resolution levels into blocks, whereby the "resolution level 0" has the block size "1×

1" and, for the following, the block size is horizontally and vertically increased by the factor R with every further size N×

N;

successively comparing, beginning with "resolution level 0", corresponding image signals of the input image signal and of the reconstructed, movement-compensated image signal, with each other, the said comparison being executed block-by-block;

switching the coding mode as soon as the difference between corresponding image signals exceeds a prescribed threshold, and forming, beginning from the current resolution level of the input image signal, the difference from the interpolated, preceding resolution level of the input image signal, whereby the interpolation is performed in multi-stage fashion, and the difference is quantized and produced as an output as soon as the difference to be formed next exceeds a prescribed threshold, whereby the difference is scalarly quantized in the "resolution level 0" and the difference is vector quantized in all other "resolution levels 1 . . . L".

2. The method according to claim 1, characterized in that the prescribed threshold (1304, 1502) is variable with the filling ratio of a buffer memory (1305, 1503).

3. A circuit arrangement for the implementation of the method according to claim 1 or 2, characterized in that the plurality of intermediate stages (13 . . . 14;

25 . . .

     26) contained n the cascade (12, 13 . . . 14, 15;

24, 25 . . . 26,

     27) amounts to two stages.

4. A circuit arrangement for the implementation of the method according to claim 1 or 2, characterized in that the plurality of intermediate stages (13 . . . 14;

25 . . .

     26) contained in the cascade (12, 13 . . . 14, 15;

24 . . . 25, 26,

     27) amounts to at least three.

5. A circuit arrangement for the implementation of the method according to claim 1 or 2, characterized in that the coder (1) contains a movement analysis unit (16) that generates an output signal (s) on the basis of a movement analysis, this output signal being used for controlling the functioning of the vector quantizing stage cascade (12, 13 . . . 14, 15).

6. The circuit arrangement according to claim 5, characterized in that the movement analysis unit (16) contains a movement segmenting unit (75) in which the image signals of a momentary image and of an image preceding this momentary image are subtracted from one another (751) and the subtraction result is successively subjected to a binary value formation unit (752), a noise suppression unit (753), a sub-scanning unit (754), an area expansion unit (755), a hole filling unit (756), an area constriction (757) and a low-pass filter in order to generate a segmenting mask signal (s).

7. A circuit arrangement for the implementation of the method according to claim 1 or 2, characterized in that codes from a code book (241) are used for signal components to be transmitted via the channel.

8. A circuit arrangement according to claim 7, characterized in that the code book is realized in the form of a ROM.

9. A circuit arrangement according to claim 7, characterized in that the code book is realized in the form of a PROM.