System for determining the code coverage of a tested program based upon static and dynamic analysis recordings

• US 4,853,851 A
• Filed: 12/16/1986
• Issued: 08/01/1989
• Est. Priority Date: 12/30/1985
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Horsch, Axel
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Phung, Danh T.
• Application Number:
  US06/942,307
• Time in Patent Office: 959 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/300, 371/19
• US Class Current: 714/38.1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3676 for coverage analysis

Abstract

System for analyzing programs by measuring the degree of code coverage of a program being tested during specific test phases. A correlation and comparison of results obtained from both a static and dynamic analysis recording is made. The introduction of a static and dynamic instruction flow indicator permits a determination of the test cover results by correlating the data of the static and dynamic instruction flow indicators. Thus, the number of untested functions can be determined during a test phase of a computer program before sending the data processing system to the field.

Claims

1. A method of measuring the ratio between the number of functions executed in a computer program during testing of said computer program with a test program, and the total number of functions in said program to be tested, comprising:

executing said test program in said computer where said number of functions are executed;

determining from each instruction address of said computer program which is called for during execution of said test program a dynamic instruction flow indicator pattern, based on the address of a current and previous executed instruction, said pattern identifying;

(a) no branch instruction, NBR;

(b) branch instruction, BR;

(c) sequential instruction, SE;

(d) non-sequential instruction, NSE;

logging said dynamic instruction flow indicator patterns as they are developed in a logging device, each pattern representing an address of an instruction which produced said pattern;

determining a static instruction flow indicator pattern for each called instruction during testing from an operational code of said called instruction, said static instruction flow indicator pattern indicating whether said instruction is;

(a) no branch instruction, NBR;

(b) branch instruction, BR;

(c) instruction reached by an internal entry (ILBL);

(d) instruction reached by an external entry (ELBL); and

comparing said static instruction flow indicator pattern with said dynamic instruction flow indicator pattern to determine a portion of all instructions of said computer program which have been tested.

2. A method as recited in claim 1 wherein the programs are tested in modules or sectors, respectively.

3. A method as recited in claim 1, wherein the dynamic and static instruction flow indicator patterns consist of 4-bit digits, with bit position 0 representing an NBR-bit, bit position 1 to the BR-bit, bit position 2 to the ILBL or the SE-bit, respectively, and bit position 3 to the ELBL or the NSE-bit, respectively.

4. A method as recited in claim 2 wherein the static and dynamic instruction flow indicator patterns (ST-IFI-PAT, D-IFI-PAT) consist of 4 bit digits, with bit position 0 being representative of the NBR-bit, bit position 1 to the BR-bit, bit position 2 to the ILBL or the SE-bit, respectively, and bit position 3 to the ELBL or the NSE-bit, respectively.

5. A method as recited in claim 1, wherein from the address of a later instruction and the address of a preceding instruction a difference is determined to identify whether the later instruction is nota branch instruction (NBR), which is the case if said difference is 1 with instructions of equal length, or n if the instruction lengths differ by the value of n, wherein a branch instruction (BR) is indicated if said difference does not equal 1 or n.

6. A method as recited in claim 2 wherein a difference between the address of a late instruction ad the address of a preceding instruction is determined, said difference determining whether the later instruction is not a branch instruction (NBR), which is the case if this difference is 1 with instructions of equal length, or n if the instruction lengths differ by the value of n, wherein a branch instruction (BR) is indicated if the difference does not equal 1 or n.

7. A method as recited in claim 3, wherein a difference between the address of an instruction and the address of a preceding instruction is determined, said difference determining whether the later instruction is not a branch instruction (NBR), which is the case if this difference is 1 with instructions of equal length, or n if the instruction lengths differ by the value of n, wherein branch instruction (BR) is indicated if the difference does not equal 1 or n.

8. A device for generating a dynamic instruction flow indicator pattern comprising:

a dynamic instruction flow indicator connected to an instruction address line, and to a clock line of a computer being run by a computer program being tested, said indicator comprising;

a first register for storing a current instruction address of said computer program being tested;

a second register, serially connected with said first register, for storing a previous instruction address of said computer program being tested;

means connected to said clock line for generating first and second clock signals, said first clock signal transferring the contents of said first register to said second register, and said second clock signal which is delayed with respect to said first clock signal transferring the instruction address from said address line to said first register;

a difference circuit connected to said first and second registers which generates a difference signal representative of whether said current and previous instructions are a no branch instruction (NBR) or a branch instruction (BR);

a third register connected to said difference circuit and controlled by a third clock signal which is delayed from said first clock signal for generating binary signals NBR and BR, wherein NBR=1 and BR=0, when said difference signal indicates a NO BRANCH instruction, and NBR=0 and BR=1 when said difference signal indicates a BRANCH instruction; and

,

a fourth register controlled by said first clock signal and receiving said binary NBR and binary BR signals, said fourth register generating additional binary signals SE and NSE, said binary signal SE=1 and NSE=0 when signal BR=1, and said signals SE=0 and NSE=1 when said signal NBR=1, whereby the binary signal value of NBR, BR, SE, and NSE constitute a dynamic instruction flow indicator pattern.

9. A device according to claim 8 further comprising:

a logging device for storing instruction flow indicator patterns, having a control storage device, said control storage device having a size related to the size of the computer program being tested, and, having a data input connected to said third and fourth registers; and

,

an address register connected to said second register for receiving an instruction address being examined, controlled by a fourth clock signal which is delayed from said third clock signal, said address register addressing said control storage device when said third and fourth registers produce a dynamic instruction flow indicator pattern.