Manchester code clock and data recovery system

• US 4,853,943 A
• Filed: 02/16/1988
• Issued: 08/01/1989
• Est. Priority Date: 02/26/1987
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Plessey Overseas Limited (Marconi Holdings Company Limited)
• Inventors: Laws, Peter G.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Huseman, Marianne
• Application Number:
  US07/156,496
• Time in Patent Office: 532 Days
• Field of Search: 375/81, 375/87, 375/110, 375/120, 329/50, 329/124
• US Class Current: 375/333
• CPC Class Codes: H03M 5/12 Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes
• CPC Class Codes: H04L 7/0066 detection of error based on transmission code rule

Abstract

A Manchester code clock and data recovery system comprises an input means which receives an encoded input signal. Data integration and error integration devices are provided which receive modified versions of the input signal and produce signals for presentation to an error modulator. The modulator generates an error signal for controlling a phase lock loop circuit having a voltage controlled oscillator.

A first output of the oscillator generates signals for controlling the data integration device over a full bit period, and for controlling the error integration device over a half bit period, in a manner that permits the clock signal to be recovered from the first output of the oscillator, and the data to be recovered from the data integration device which is arranged to generate a Manchester biphase coded signal.

Claims

1. A Manchester code clock and data recovery system, comprising input means for receiving an encoded input signal having clock and data dependent transitions, a signal modulator connected to the input means, integration means for receiving modulated versions of the input signal from the signal modulator including a data integrator to which the signal modulator is connected and from which a Manchester biphase coded signal is generated and an error integrator connected to the input means, error modulation means connected to the data integrator and the error integrator for producing an error signal, loop circuit means connected to the error modulation means and the integration means for obtaining correct phase lock on the encoded input signal by distinguishing between said clock and data dependent transitions in the encoded input signal under control of the error signal, including a voltage controlled oscillator, first output means operatively connecting the voltage controlled oscillator to the data integrator for sampling over substantially a full bit period, and second output means operatively connecting the voltage controlled oscillator to the error integrator for sampling over substantially a half bit period to enable recovery of a clock signal from the first output means reflecting said clock dependent transitions in the encoded input signal and recovery of data from the Manchester biphase coded signal generated by the data integrator.

2. A Manchester code clock and data recovery system as claimed in claim 1, including data processing means connected to the data integrator for receiving the Manchester biphase coded signal from which transition polarity of two successive bit periods is translated into data, and a non-return to zero output data signal is generated.

3. A Manchester code clock and data recovery system as claimed in claims 1 or 2, including error amplifier and filter means interconnecting the error modulation means with the voltage controlled oscillator for feedback of the error signal in the phase lock loop circuit means.

4. A Manchester code clock and data recovery system as claimed in claim 3, wherein the input means is a limiting amplifier.

5. A Manchester code clock and data recovery system as claimed in claim 4, wherein the second output means includes a quadrature clock circuit through which a clock control signal fed to the error integrator from the voltage controlled oscillator is phase-shifted by substantially 90°

.

6. A Manchester code clock and data recovery system as claimed in claim 5, including detector means connected to the data integrator for generating output signals indicative of a phase lock condition.