Method of making multilayer pc board using polymer thick films

• US 4,854,040 A
• Filed: 06/27/1988
• Issued: 08/08/1989
• Est. Priority Date: 04/03/1987
• Status: Expired due to Fees

• Current Assignee: Joseph A. Turek
• Original Assignee: Poly Circuits, Inc.
• Inventors: Turek, Joseph A.
• Primary Examiner(s): Eley, Timothy V.
• Application Number:
  US07/212,321
• Time in Patent Office: 407 Days
• Field of Search: 29/846, 29/825, 29/852, 29/841, 29/831, 29/847, 29/830
• US Class Current: 29/847
• CPC Class Codes: H05K 1/095 for polymer thick films, i.e. having a permanent organic polymeric binder
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0209 Inorganic, non-metallic particles
• CPC Class Codes: H05K 2201/092 Exposing inner circuit layers or metal planes at the walls of high aspect ratio holes
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2203/044 Solder dip coating, i.e. coating printed conductors, e.g. pads by dipping in molten solder or by wave soldering
• CPC Class Codes: H05K 2203/0571 Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
• CPC Class Codes: H05K 2203/1394 Covering open PTHs, e.g. by dry film resist or by metal disc
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/3447 Lead-in-hole components H05K3/3415 takes precedence
• CPC Class Codes: H05K 3/3452 Solder masks
• CPC Class Codes: H05K 3/3468 Applying molten solder
• CPC Class Codes: H05K 3/3473 Plating of solder
• CPC Class Codes: H05K 3/427 initial plating of through-holes in metal-clad substrates
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4664 Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders H05K3/4647 takes precedence
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A multilayer printed circuit board which reliably and economically marries conventional copper clad printed circuit board technology with polymeric conductors and insulators. Reliability is enhanced by forming all solder pads of copper, providing conductive tails on solder pads which are to be connected by polymeric inks, and ultimately forming a solder resist over all but the solder pads. As a result, polymer inks can be applied to both sides of the board, and the completed board can be subject to conventional solder dipping or wave soldering operations. According to one feature of the invention, a thin dielectric layer can be applied as intermediate to planar conductive layers which form a power plane having built-in distributed capacitance for decoupling.

Claims

1. A method of producing a multiple layer circuit board, for mounting and electrically connecting a plurality of components, the method comprising the steps of

providing a supporting substrate having copper layer on at least one side thereof,

etching said copper layer to produce an array of solder pads for receiving said components to be mounted on the circuit board,

said step of etching including forming conductive tails in the copper layer connected to the solder pads for providing protected electrical connections thereto,

depositing a dielectric layer over the copper layer while leaving said tails and pads exposed to insulate the copper layer except for said tails and pads,

applying conductive polymer traces between selected ones of said tails, thereby to electrically interconnect the associated solder pads,

applying a solder mask over the polymer layers leaving said pads exposed but covering said tails thereby to shield the polymer, and

solder dipping the completed circuit board to apply a layer of solder to said exposed solder pads.

2. The method of claim 1, wherein multiple alternating layers of conductive polymer and dielectric are deposited, said layer of conductive polymer patterned to interconnect selected ones of said solder pads and said dielectric layer leaving said solder pads and at least some of said conductive tails exposed.

3. The method of claim 2, wherein multiple alternating layers of conductive polymer and dielectric are deposited on both surfaces of said circuit board.

4. The method of claim 1, comprising the additional step providing at least one array of holes, said holes penetrating said solder pads to receive conductive leads of the circuit components so that said leads can be soldered to said solder pads.

5. The method of claim 3, wherein at least some of said solder pads remain undrilled and thereby adapted to receive surface mounted components, said pads being interconnected by conductive polymer traces and said pads and said traces being sealingly covered by said solder resist.

6. A process for manufacturing a multilayer circuit board comprising the steps of providing a substrate having a conductive layer on at least one side, providing an array of solder pads on said substrate adapted to receive electrical components to be mounted on said circuit board, depositing multiple circuit layers in alternating sequence with multiple insulating layers on a first surface of said substrate, the multiple circuit layers connecting selected ones of said solder pads, and depositing a distributed decoupling system on a second surface of said substrate, in which the step of distributed decoupling system deposition comprises:

providing a first planar conductive layer having conductive connections to only selected ones of the solder pads for providing a first power connection thereto,

depositing a thin dielectric film over the planar conductive layer,

depositing a second planar conductive layer comprising a film of conductive polymer over the thin dielectric layer, the second planar conductive layer having connections to selected ones of the solder pads for providing a second power connection thereto, and

depositing a mask of solder resist over the second planar layer for protection thereof, said mask of solder resist being deposited to leave at least some of the solder pads exposed for a subsequent soldering operation.

7. The process of claim 6, wherein the step of providing a substrate having a conductive layer on at least one side includes etching the conductive layer to form the array of solder pads, and the step of providing said first planar conductive layer includes providing conductive connections to selected ones and isolated from the others of the solder pads.

8. The process of claim 6, wherein the step of providing a substrate having a conductive layer on at least one side includes depositing a first conductive polymer layer connected to selected ones of said solder pads for coupling power thereto.

9. The process of claim 6, wherein the step of depositing a distributed decoupling system is completed over multiple alternating layers of conductive polymer and dielectric and said first conductive layer of said distributed decoupling system is connected to selected ones of said solder pads and isolated from others.

10. The process of claim 6, wherein multiple alternating layers of conductive polymer and dielectric are deposited over said distributed decoupling system.