Selectively definable semiconductor device

• US 4,855,803 A
• Filed: 07/26/1988
• Issued: 08/08/1989
• Est. Priority Date: 09/02/1985
• Status: Expired due to Term

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Azumai, Hideo, Fujii, Koichi, Yoshioka, Keiichi, Seigenji, Takashi
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): NGO, NGAN V
• Application Number:
  US07/224,268
• Time in Patent Office: 378 Days
• Field of Search: 357/45, 357/45 M, 357/40, 357/41, 365/95, 365/96, 365/63, 365/154, 365/156, 365/103, 365/104
• US Class Current: 257/202
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

A selectively definable semiconductor device is provided. In one form, a composite gate array includes a plurality of logic dedicated general purpose cell regions and a plurality of function dedicated cell regions each of which is disposed between the two corresponding ones of the plurality of logic dedicated general purpose cell regions, whereby each of the cell regions may be used as an interconnection region selectively. In another form, a semiconductor memory device which may be selectively defined as a ROM or a RAM by a metalization process is provided.

Claims

1. A composite gate-array semiconductor device, comprising:

a plurality of logic dedicated general purpose cell regions, each capable of providing a desired logic function and also capable of providing an interconnection function selectively;

a plurality of function dedicated cell regions, each capable of providing a desired function and also capable of providing an interconnection function selectively, each of said plurality of function dedicated cell regions being disposed between two corresponding ones of said plurality of logic dedicated general purpose cell regions;

a pair of adjacent bit lines;

wherein said plurality of function dedicated cell regions include a plurality of RAM/ROM cells which can be selectively defined either as RAM cells or as ROM cells by metallization and which are connected to said adjacent bit lines; and

a one-bit decoder which is connected between said pair of adjacent bit lines when said plurality of RAM/ROM cells are defined as ROM cells.

2. The device of claim 1 wherein said regions, each elongated in shape, are arranged in a row spaced apart from each other.

3. The device of claim 1 wherein at least some of said plurality of logic dedicated general purpose cell regions are interconnected by some of said plurality of function dedicated cell regions to define a desired random logic function, whereby said some of said plurality of function dedicated cell regions serve as interconnection regions.

4. The device of claim 1 wherein at least one of said plurality of function dedicated cell regions has a function as a memory, D/A converter, operational amplifier or arithmetic logic unit.

5. The device of claim 1 wherein said plurality of function dedicated cell regions include a plurality of RAM cells arranged in a plurality of rows;

a plurality of first X decoders each provided for each row of said plurality of RAM cells;

a Y decoder operatively associated with each of said plurality of RAM cells;

a sense circuit operatively associated with said Y decoder; and

a R/W control circuit operatively associated with said sense circuit.

6. The device of claim 5 wherein said plurality of logic dedicated general purpose cell regions include a second X decoder operatively associated with each of said plurality of first X decoders.

7. The device of claim 6 wherein said plurality of logic dedicated general purpose cell regions further include an address buffer which is operatively associated with said second X decoder and said Y decoder.