AM digital demodulator

• US 4,857,859 A
• Filed: 06/17/1988
• Issued: 08/15/1989
• Est. Priority Date: 06/18/1987
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Kenwood (JVC Kenwood Corporation)
• Original Assignee: Kabushiki Kaisha Kenwood (JVC Kenwood Corporation)
• Inventors: Nakazawa, Akira, Asahi, Nobumitsu
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/208,134
• Time in Patent Office: 424 Days
• Field of Search: 329/104, 329/109, 329/145, 455/201-204, 455/337, 375/41, 375/43, 375/77, 375/94
• US Class Current: 329/363
• CPC Class Codes: H03D 1/02 Details

Abstract

An AM demodulator of a digital signal processing type wherein an analog AM signal is converted to a digital AM signal, the digital AM signal is squared and a one sample-delayed version of the digital AM signal is squared, these squared signals are added, and the square root of the resulting sum of the squared signals is extracted as an AM demodulated signal. The demodulator comprises a detector for detecting the level of a sum signal representing the sum of the squared signals, an upward bit shifter for bit shifting upwardly the sum signal on the basis of the detection output from the level detector, a polynomial calculator for approximately extracting the square root of the sum signal, and a downward bit shifter for bit shifting downwardly the output signal from the polynomial calculator.

Claims

1. An AM demodulator of a digital signal processing type wherein an analog AM signal is converted to a digital AM signal, the digital AM signal is squared and a one sample-delayed version of the digital AM signal is squared, these squared signals are added, and the square root of the resulting sum of the squared signals is extracted as an AM demodulated signal, comprising:

a level detector for detecting the level of a sum signal representing the sum of the squared signals;

an upward bit shifter for bit shifting upwardly the sum signal on the basis of the output from the level detector to correct the level of the sum signal;

a polynomial calculator for approximately extracting the square root of the level corrected sum signal; and

a downward bit shifter for bit shifting downwardly the output signal from the polynomial calculator to correct the level of the just mentioned output signal.

2. A digital AM demodulator according to claim 1, wherein fixed constants used in the polynomial calculator are coefficients of a polynomial having a limited order obtained by Taylor expansion of a square root function.

3. A digital AM demodulator according to claim 1 or 2, wherein the polynomial calculator provides a square root output having the highest approximation for an input signal in a range of from 0.25 to 1.

4. A digital AM demodulator according to claim 1 or 2 wherein when the quantity of bit shift at the upward bit shifter is 2n bits, the quantity of bit shift at the downward bit shifter is n bits.

5. A digital AM demodulator according to claim 3, wherein when the quantity of bit shift at the upward bit shifter is 2 bits, the quantity of bit shift at the downward bit shifter is n bits.