MOS IC reverse battery protection

• US 4,857,985 A
• Filed: 12/15/1988
• Issued: 08/15/1989
• Est. Priority Date: 08/31/1987
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Miller, William E.
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US07/285,290
• Time in Patent Office: 243 Days
• Field of Search: 357/42, 357/48, 361/82, 361/100, 361/246, 307/304, 307/127, 363/127
• US Class Current: 307/127
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H02H 11/003 using a field effect transistor as protecting element in one of the supply lines
• CPC Class Codes: H02H 3/18 responsive to reversal of direct current

Abstract

A field effect transistor has its drain and source regions connected between one of the two supply pads of an operative integrated circuit, the gate of the field effect transistor being connected to the other pad such that the gate is negatively biased during reverse battery to prevent current flow through the circuit in this condition and, hence, to prevent destruction of the circuit. The FET is sized to have minimal voltage drop during normal, forward battery operation of the circuit. The FET can be implemented as either an N-channel or a P-channel device.

Claims

1. In an integrated circuit which includes a power supply pad and a ground pad, one or more operative circuits to be protected from reverse voltage being connected between the power supply pad and the ground pad via a power supply distribution bus and a ground supply distribution bus, and wherein, under normal operating conditions, a battery is connected between the power supply pad and the ground pad such that the power supply pad provides a positive supply voltage to said operative circuit or circuits to be protected from reverse voltage, the improvement comprising a MOS field-effect transistor having its drain and source regions connected between said operative circuit or circuits to be protected from reverse voltage and one of the pads, the gate of the field effect transistor being connected to the other pad such that the gate of the field effect transistor is turned off during a reverse battery condition, the body of the field-effect transistor being connected to the source/drain node which is connected to said operative circuit or circuits to be protected from reverse voltage, preventing current flow through said operative circuit or circuits to be protected from reverse voltage.

2. The integrated circuit according to claim 1 wherein the field effect transistor has a voltage drop across it of about 0.1 volts during maximum current flow through said operative circuit or circuits to be protected from reverse voltage in a forward battery condition.

3. The integrated circuit according to claim 1 wherein the field effect transistor is an N-channel device having its drain and source connected between said operative circuit or circuits to be protected from reverse voltage and the ground pad, and in series between the ground pad and the ground supply distribution bus, its gate connected to the power supply pad, and its body connected to the source/drain node which is connected to said operative circuit or circuits to be protected from reverse voltage.

4. The integrated circuit according to claim 1 wherein the field effect transistor is a P-channel device having its drain and source connected between said operative circuit or circuits to be protected from reverse voltage and the power supply pad, and in series between the power supply pad and the power supply distribution bus, its gate connected to the ground pad, and its body connected to the source/drain node which is connected to said operative circuit or circuits to be protected from reverse voltage.