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Reconfigurable pipelined processor

  • US 4,858,113 A
  • Filed: 04/10/1987
  • Issued: 08/15/1989
  • Est. Priority Date: 04/10/1987
  • Status: Expired due to Fees
First Claim
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1. A reconfigurable pipelined processor for processing data, comprising:

  • (a) a plurality of memory devices for storing bits of data;

    (b) a plurality of arithmetic units for performing arithmetic functions with the data;

    (c) cross bar means for connecting said memory devices with said arithmetic units for transferring data therebetween;

    (d) at least one counter connected with said cross bar means for providing a source of addresses to said memory devices;

    (e) at least one variable tick delay device connected with each of said memory devices and arithmetic units; and

    (f) means for providing control bits to said variable tick delay device for variably controlling the input and output operations thereof to selectively delay said memory devices and arithmetic units to align the data for processing in a selected sequence.

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