Fabrication of high resistive loads utilizing a single level polycide process

• US 4,859,278 A
• Filed: 08/11/1988
• Issued: 08/22/1989
• Est. Priority Date: 08/11/1988
• Status: Expired due to Fees

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Choi, Francis K.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US07/231,404
• Time in Patent Office: 376 Days
• Field of Search: 437/34, 437/41, 437/45, 437/56, 437/57, 437/58, 437/59, 437/196, 437/200, 437/201, 156/643, 156/646, 156/652, 156/656, 156/657, 156/659.1, 156/661.1, 156/653, 156/662, 357/23.1, 357/23.9, 357/23.11, 357/23.13, 357/41, 357/42, 357/44, 357/59, 357/49
• US Class Current: 438/238
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 28/20 Resistors

Abstract

This invention relates to a method of fabricating high resistive loads utilizing a single level polycide process in very large scale integrated circuits. By etching away a top silicide layer which exposes an underlying polysilicon layer and then implanting with a heavy dose of boron, a high resistive load on the integrated circuit is formed. Very often the highly resistive polysilicon load is implemented as a second polysilicon layer, which increases the process complexity vastly. This invention discloses the use of only one polycide layer to implement both the low resistive gate and interconnect and the high resistive polysilicon load needed to implement certain circuit functions.

Claims

1. A method of fabricating high resistive loads in a very large scale integrated circuit comprising

depositing an undoped layer of polysilicon over a predetermined area of said integrated circuit,

doping said layer of polysilicon to render it conductive,

depositing a layer of metallic silicide on said polysilicon layer to form a layer generally termed a polycide layer,

masking and etching said polycide layer to form the gates and interconnect links,

implanting said gate areas to form the source/drain areas of said integrated circuit,

masking and etching said polycide layer to expose an area of said polycide wherein said silicide layer is etched away at said exposed area down to the polysilicon layer, and

implanting said exposed area of polysilicon with a heavy dose of boron to fabricate said high resistive load element.

2. A method of fabricating high resistive loads in a very large scale integrated circuit comprising

depositing an undoped layer of polysilicon over a predetermined area of said integrated circuit,

doping said layer of polysilicon to render it conductive,

masking and etching said polycide layer to form the gates and interconnect links,

oxide depositing and anisotropic etching said gates and interconnecting links to form oxide spacers in the gate and interconnect link areas next to the polysilicon layers,

implanting said gate areas to form the source/drain areas of said integrated circuit,

masking and etching said polysilicon layer to define an area of said polysilicon with photoresist material,

depositing a metallic silicide on said polysilicon layer with photoresist to form an metal overhanging area on the desirable resistive region amd a layer layer generally termed polycide layer elsewhere,

removing said photoresist material defining said area, and

implanting said defined area of polysilicon with a heavy dose of boron to fabricate said high resistive load element.