Digital selective calling receiver having a selectively attachable device for multiple independent address decoding capability

• US 4,860,004 A
• Filed: 01/04/1988
• Issued: 08/22/1989
• Est. Priority Date: 01/04/1988
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Davis, Walter L.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Pudpud, E. O.
• Application Number:
  US07/140,455
• Time in Patent Office: 596 Days
• Field of Search: 340/825.44, 340/825.52, 340/825.48, 340/825.2, 340/825.47, 340/825.21, 340/311.1, 455/346, 455/349, 361/392, 361/393, 361/404, 379/56, 379/57, 379/58
• US Class Current: 340/7.45
• CPC Class Codes: G08B 5/22 using electric transmission; using electromagnetic transmission
• CPC Class Codes: G08B 5/229 with other provisions not elsewhere provided for
• CPC Class Codes: H04W 8/245 from a network towards a terminal
• CPC Class Codes: H04W 88/022 Selective call receivers

Abstract

A digital selective call receiver is modified to enhance the address decoding capability by providing access to received data, bit and frame synchronization signals, and a detect input terminal of an annunciator. A selectively attachable additional independent address decoding device including additional memory and an independent address decoder operating in parallel with the decoder in the selective call receiver is attached to the receiver for accessing the various signals and providing a detect signal to the annunicator when an additional independent address is decoded.

Claims

1. In a digital selective call receiver including a receiver circuit for receiving transmitted signals, and a decoder for decoding said received signals, said decoder comprising:

a memory containing a digital sequence corresponding to one address of the receiver;

means for generating bit and frame synchronization signals;

a comparator coupled to the receiver circuit and memory and governed by the bit and frame synchronization signals to determine correspondence between the receiver signals and the digital sequence stored in said memory; and

annunciator responsive to the comparator for alerting the user of such correspondence which is indicative of the reception of a selective call message, a selectively attachable additional independent address decoding device comprising;

additional memory means containing at least one additional independent digital sequence address; and

additional decoder means operative in parallel with said decoder for independently decoding received signals including

additional comparator means coupled between the receiver circuit and said additional memory means, and governed by the bit and frame synchronization signals of the decoder to determine correspondence between the received signals and the additional independent digital sequence address, and for providing a separate signal to the annunciator for alerting the user of such correspondence which is indicative of the reception of a selective call message corresponding to the at least one additional independent digital sequence address.

2. The selectively attachable decoding device of claim 1 wherein the additional memory means is contiguous with said memory.

3. The selectively attachable decoding device of claim 1 further including means for generating an additional signal and providing said signal to said annunciation means to distinguish the detection of at least one additional independent address.

4. The selectively attachable decoding device of claim 3 wherein said decoder further includes means to detect the reception of functional code words which are not independent of the additional independent address and supply signals representative of the detected functional code words to the annunciator.

5. A digital selective call receiver including a receiver circuit for receiving transmitted signals, and a decoder for decoding said received signals, said decoder comprising a memory containing a digital sequence corresponding to one address of the receiver;

means for generating bit and frame synchronization signals;

a comparator coupled to the receiver circuit and memory and governed by the bit and frame synchronization signals to determine correspondence between the received signals and the digital sequence stored in said memory;

an annunciator responsive to the comparator for alerting the user of such correspondence which is indicative of the reception of a selective call message; and

means for electrically coupling another selectively attachable independent address decoding device which is operative in parallel with said decoder, said electrical coupling means comprising;

means for rendering said bit and frame synchronization signals electrically accessible to said another decoder device from said decoder;

means for rendering said received signals electrically accessible to said another decoder device from said receiver circuit; and

means for rendering an input terminal of said annunciator electrically accessible to a detect signal from said another decoder device.

6. The digital selective call receiver of claim 5 further including means for rendering aid annunciator electrically accessible to signals of the another decoder device which indicate the reception of code words which are not independent of an additional independent address of the another decoder device.

7. The digital selective call receiver of claim 5 further including means for rendering said annunciator electrically accessible to an additional signal from said another decoder device.

8. A selectively attachable additional independent address decoding device for attachment to a digital selective call receiver, said receiver including a receiver circuit for receiving transmitted signals, and a decoder for decoding said received signals, said decoder comprising:

a memory containing a digital sequence corresponding to the address of a specific receiver;

means for generating bit and frame synchronization signals;

a comparator coupled to the receiver circuit and memory and governed by the bit and frame synchronization signals to determine correspondence between the received signals and the digital sequence stored in said memory, and an annunciator responsive to the comparator for alerting the user of the reception of a selective call message, said additional decoding device comprising;

additional memory means containing at least one additional independent digital sequence address; and

additional decoder means operative in parallel with said decoder for independently decoding received signals including

additional comparator means coupled between said receiver circuit and said additional memory means, and governed by the bit and frame synchronization signals of the decoder to determine correspondence between the received signals and the additional independent digital sequence address, and for providing a separate signal to the annunciator to alert the user of the reception of a received signal corresponding to the additional independent digital sequence address.