Semiconductor device MOSFET with V-shaped drain contact

• US 4,860,084 A
• Filed: 01/03/1989
• Issued: 08/22/1989
• Est. Priority Date: 09/03/1984
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shibata, Tadashi
• Primary Examiner(s): Mintel, William A.
• Application Number:
  US07/293,570
• Time in Patent Office: 231 Days
• Field of Search: 357/55, 357/68, 357/23.14, 357/23.11, 357/23.1, 357/23.6, 357/71, 357/23.8, 357/23.4
• US Class Current: 257/288
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A concave portion having a V-shaped cross section is formed in a contact region of a p-type silicon substrate. The contact region is defined by a hole formed in an insulative layer formed over the substrate. An n-type diffusion layer is formed in the substrate so as to surround the concave portion. The n-type diffusion layer is connected to a drain region of a FET. A metal layer is formed on the insulative layer such that the metal layer is in electric contact with the diffusion layer through the increased surface area of the concave portion in the contact region.

Claims

1. A metal oxide semiconductor field effect transistor formed on a semiconductive substrate of a first conductivity type having a surface, said transistor comprising:

(a) a conductive gate electrode layer insulatively provided above said substrate;

(b) first and second semiconductive layers of a second conductivity type, which are formed in the surface of said substrate to serve as source and drain regions of said transistor, said substrate having first and second concave portions formed to have inner surfaces and bottom portions, said first and second concave portions being adjacent to said first and second semiconductive layers, respectively and said first and second semiconductive layers including contact portions which extend below the bottom portions of said first and second concave portions to surround said first and second concave portions, respectively;

(c) an insulative layer formed on said substrate defining therein contact holes for said source and drain regions;

(d) first and second conductive wiring layers which are formed on said insulative layer to cover said contact holes in such a manner that they are electrically in contact with said first and second semiconductive layers through said concave portions, respectively; and

(e) third and fourth semiconductive layers of the first conductivity type, which are formed in said substrate to surround said contact portions of said first and second semiconductive layers, respectively, for suppressing current charges from leaking from said first and second concave portions, thereby preventing the occurrence of punch-through phenomenon in said transistor, said third and fourth semiconductive layers being formed by doping inpurities of the first conductivity type in said substrate through said contact holes.

2. The device according to claim 1, wherein each of said first and second conductive wiring layers has a double-layered structure.

3. The device according to claim 1, wherein each of said first and second conductive wiring layers comprises:

a first metal layer buried in the corresponding concave portion; and

a second metal layer which is insulatively provided above said substrate and which is stacked on said first metal layer so as to be electrically connected with said first metal layer.

4. The device according to claim 1, wherein said first and second concave portions have a V-shaped cross section.