Microprocessor system

• US 4,860,198 A
• Filed: 05/17/1988
• Issued: 08/22/1989
• Est. Priority Date: 01/31/1985
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takenaka, Tsutomu
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US07/196,752
• Time in Patent Office: 462 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/307
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A microprocessor system is configured by connecting an n/2-bit memory and/or I/O to an n-bit microprocessor. The system has a read/write controller for enabling/disabling a read/write control signal for accessing the memory and/or I/O, an address latch counter for latching and updating the address, a bus converter for converting the data bus through which the data is transferred, and a timing generator. The timing generator comprises a detector for detecting that the instruction executed by the microprocessor is a word transfer instruction for the memory and/or I/O, a counter for counting the number of times a read/write control signal is generated and a timing controller for generating various timing control signals when the word transfer instruction for the memory and/or I/O is executed. When the microprocessor performs the word transfer instruction for the memory and/or I/O, the read/write control signal is enabled and disabled to perform two access cycles. The word transfer instruction can be automatically converted to two 1/2 transfer instructions.

Claims

1. A microprocessor system comprising:

microprocessor means, coupled to a first 2n-bit data bus and a first control bus, said first 2n-bit data bus including first and second data buses each having an n-bit data width, and responsive to an input 2n-bit data transfer command, for outputting a transfer instruction onto said first control bus, for selectively inputting into said microprocessor means 2n-bit input data on said first 2n-bit data bus, and for selectively outputting from said microprocessor means 2n-bit output data onto said first 2n-bit data bus, an operation state of said microprocessor means being held in accordance with a wait instruction input thereto;

read/write control means, coupled to said first control bus and a second control bus and responsive to the transfer instruction from said microprocessor means and a disable instruction input thereto, for selectively and sequentially generating and outputting onto said second control bus first and second transfer instructions, the first and second transfer instructions being associated with first and second transfer cycles, respectively;

bus converter means, coupled to said first 2n-bit data bus and a second 2n-bit data bus including third and fourth data buses and responsive to an input bus conversion instruction, for selectively and sequentially inputting into said bus converter means first n-bit input data ("FNID") and second n-bit input data ("SNID") on said third data bus, for substantially simultaneously outputting from said bus converter means the FNID and SNID as the 2n-bit input data onto said first 2n-bit data bus, for selectively inputting into said bus converter means the 2n-bit output data comprising first n-bit output data ("FNOD") and second n-bit output data ("SNOD") on said first 2n-bit data bus, and for sequentially outputting from said bus converter means the FNOD and the SNOD onto said third data bus;

a device having the n-bit data width, coupled to said third data bus and said second control bus and responsive to the first and second transfer instructions, for selectively and sequentially outputting from said device the FNID and SNID onto said third data bus, and for selectively and sequentially inputting into said device the FNOD and the SNOD on said third data bus; and

timing generating means, coupled to said second control bus and responsive to the first and second transfer instructions from said read/write control means and an input address, for generating and outputting to said bus converter means the bus conversion instruction, for generating and outputting to said read/write control means the disable instruction between the first and second transfer cycles, and for generating and outputting to said microprocessor means the wait instruction from a first timing during the first transfer cycle to a second timing during the second transfer cycle.

2. The system according to claim 1, wherein said bus converter means comprises:

first transfer means, coupled to said first data bus and said third data bus, for selectively inputting into said first transfer means the FNID on said third data bus in accordance with an input first instruction to hold the FNID, for selectively outputting the held data onto said first data bus in accordance with an input second instruction, and for selectively transferring the FNOD from said first data bus onto said third data bus in accordance with an input third instruction;

second transfer means, coupled to said second data bus and said fourth data bus, for selectively transferring the SNID from said fourth data bus onto said second data bus in accordance with an input fourth instruction, and for selectively transferring the SNOD from said second data bus onto said fourth data bus in accordance with an input fifth instruction; and

third transfer means, coupled to said third data bus and said fourth data bus, for selectively transferring one of the FNID and the SNID from said third data bus onto said fourth data bus in accordance with an input sixth instruction, and for selectively transferring the SNOD from said fourth data bus onto said third data bus in accordance with an input seventh instruction, and

said timing generating means includes means responsive to the first and second transfer instructions and the address, for selectively generating one of a first set including the first instruction in the first transfer cycle and the second, fourth, and sixth instructions in the second transfer cycle and a second set including the third instruction in the first transfer cycle and the fifth and seventh instructions, and for outputting the generated set as the bus conversion instruction to said bus converter means.

3. The system according to claim 2, wherein said first transfer means further comprises means for selectively transferring the SNID from said third data bus onto said first data bus in accordance with an input eighth instruction, said second transfer means further comprises means for selectively inputting the FNID on said fourth data bus in accordance with an input ninth instruction to hold the FNID and for selectively outputting the held data onto said second data bus in accordance with an input tenth instruction, and said timing generating means includes means responsive to the first and second transfer instructions and a least significant bit of the address, for selectively generating one of a third set including the sixth and ninth instructions in the first transfer cycle and the eighth and tenth instructions in the second transfer cycle, and a fourth set including the fifth and seventh instructions in the first transfer cycle and the third instruction in the second transfer cycle.

4. The system according to claim 1, further comprising an address bus coupled to said device, and address latch counter means for latching the address from said microprocessor means in accordance with an input latch instruction and for outputting the latched address to said device and said timing generating means, and wherein said read/write control means further comprises means for generating the latch instruction in accordance with the transfer instruction from said microprocessor means to output the generated latch instruction to said address latch counter means.

5. The system according to claim 4, wherein said address latch counter means further comprises means for updating the latched address by one in accordance with an input update instruction and for outputting the updated address to said timing generating means and onto said address bus, and said timing generating means further comprises means for generating the update instruction between the first and second transfer cycles to output the generated instruction to said address latch counter means.

6. The system according to claim 5, wherein said address latch counter means comprises:

latch means for latching the address output from said microprocessor means in accordance with the latch instruction and for outputting the latched address onto said address bus; and

counter means for updating the latched address by one in accordance with the update instruction and for outputting the updated address to said timing generating means and onto said address bus.

7. The system according to claim 5, wherein the FNID and the FNOD are associated with an even address, the SNID and the SNOD are associated with an odd address subsequent to the even address, and said address latch counter means comprises:

latch means for latching the address output from said microprocessor means in accordance with the latch instruction and for outputting the latched address to said timing generating means and onto said address bus; and

gate means for calculating logical OR of a least significant bit of the latched address and a bit indicated by the input update instruction and for outputting the latched address except for the least significant bit and the calculated bit.

8. The system according to claim 5, further comprising a second device having a 2n-bit data width and coupled to said second 2n-bit data bus, said second control bus, and said address bus, and wherein said timing generating means comprises detecting means for detecting whether or not the latched address from said address latch counter means addresses to said second device, means for inhibiting said timing generating means from generating the disable instruction, the wait instruction, and the update instruction, said read/write control means not generating the second transfer instruction, said address latch counter means not updating the latched address, and said microprocessor means being not held, and means for generating a second bus conversion instruction in accordance with the first transfer instruction when it is detected that the latched address addresses to said second device, and said bus converter means further comprises means responsive to an input second bus conversion instruction, for selectively transferring the 2n-bit output data from said first 2n-bit data bus onto said second 2n-bit data bus, and for selectively transferring the 2n-bit input data from said second 2n-bit data bus onto said first 2n-bit data bus.

9. A data transfer apparatus comprising:

bus converter means, coupled to a first 2n-bit data bus including first and second data buses, each of said first and second data buses having an n-bit data width, and to a third data bus having the n-bit data width, and responsive to an input first conversion instruction, for selectively and sequentially inputting into said bus converter means first n-bit input data ("FNID") and second n-bit input data ("SNID") on said third data bus, and for substantially simultaneously outputting from said bus converter means the FNID and SNID as the 2n-bit input data onto said first 2n-bit data bus; and

timing generating means, responsive to input first and second transfer instructions and an input address, the address being associated with the FNID and SNID, for generating and outputting to said bus converter means the first bus conversion instruction and for generating a disable instruction between first and second transfer cycles, the first and second transfer cycles being associated with the first and second transfer instructions, respectively;

read/write control means, responsive to an input 2n-bit data transfer instruction and to the disable instruction input from said timing generating means, for selectively and sequentially generating and outputting to said timing generating means the first and second transfer instructions.

10. The apparatus according to claim 9, wherein said bus converter means comprises:

first transfer means, coupled to said first data bus and said third data bus, for selectively inputting from said first transfer means the FNID on said third data bus in accordance with an input first instruction to hold the FNID and for selectively outputting the held data onto said first data bus in accordance with an input second instruction; and

second transfer means, coupled to said second data bus and said third data bus, for selectively transferring the SNID from said third data bus onto said second data bus in accordance with an input third instruction, and

said timing generating means includes means, responsive to the first and second transfer instructions and the address, for selectively generating the first conversion instruction including the first instruction in the first transfer cycle and the second and third instructions in the second transfer cycle and for outputting the first conversion instruction to said bus converter means.

11. The apparatus according to claim 9, wherein said bus converter means comprises:

third transfer means, coupled to said second data bus and said third data bus, for selectively inputting into said third transfer means the FNID on said third data bus in accordance with an input fourth instruction to hold the FNID and for selectively outputting the held data onto said second data bus in accordance with an input fifth instruction; and

fourth transfer means, coupled to said first data bus and said third data bus, for selectively transferring the SNID from said third data bus onto said first data bus in accordance with an input sixth instruction, and

said timing generating means includes means, responsive to the first and second transfer instructions and the address, for selectively generating the first conversion instruction including the fourth instruction in the first transfer cycle and the fifth and sixth instructions in the second transfer cycle and for outputting the first conversion instruction to said bus converter means.

12. The apparatus according to claim 9, wherein said bus converter means further comprises first means for selectively and sequentially transferring 2n-bit output data including first n-bit output data ("FNOD") on said first data bus and second n-bit output data ("SNOD") on said second data bus, in units of the n-bit data in accordance with an input second conversion instruction;

and

said timing generating means further comprises second means for selectively generating the second conversion instruction in accordance with the first and second transfer instructions to output the generated instruction to said bus conversion means.

13. The apparatus according to claim 12, wherein said first means comprises:

fifth transfer means, coupled to said first data bus and said third data bus, for selectively transferring the FNOD from said first data bus onto said third data bus in accordance with an input seventh instruction; and

sixth transfer means, coupled to said second data bus and said third data bus, for selectively transferring the SNOD from said second data bus onto said third data bus in accordance with an input eighth instruction, and

said timing generating means includes means, responsive to the first and second transfer instructions and an input second address, the second address being associated with the FNOD and SNOD, for selectively generating the second conversion instruction including the seventh instruction in the first transfer cycle and the eighth instruction in the second transfer cycle, and for outputting the first conversion instruction to said bus converter means.

14. The apparatus according to claim 12, wherein said first means comprises:

fifth transfer means, coupled to said first data bus and said third data bus, for selectively transferring the FNOD from said first data bus onto said third data bus in accordance with an input seventh instruction; and

sixth transfer means, coupled to said second data bus and said third data bus, for selectively transferring the SNOD from said second data bus onto said third data bus in accordance with an input eighth instruction, and said timing generating means includes means, responsive to the first and second transfer instructions and the second address, for selectively generating the second conversion instruction including the eighth instruction in the first transfer cycle and the seventh instruction in the second transfer cycle, and for outputting the first conversion instruction to said bus converter means.

15. The apparatus according to claim 9, wherein said bus converter means further comprises third means, responsive to an input third conversion instruction, for selectively inputting into said bus converter means 2n-bit output data on said first 2n-bit data bus, for holding one of FNOD and SNOD of 2n-bit output data, for selectively transferring the other of the FNOD and SNOD onto said third data bus, and for outputting the held data onto said third data bus;

and

timing generating means further comprises fourth means, responsive to input first and second transfer instructions and the second address, for generating and outputting to said bus converter means the third bus conversion instruction to output the generated instruction to said bus converter means.

16. The apparatus according to claim 15, wherein said third means comprises:

seventh transfer means, coupled to said second data bus and said third data bus, for selectively inputting into said seventh transfer means the SNOD on said second data bus in accordance with an input ninth instruction to hold the SNOD and for selectively outputting the held data onto said first data bus in accordance with an input tenth instruction; and

eighth transfer means, coupled to said first data bus and said third data bus, for selectively transferring the FNOD from said first data bus onto said third data bus in accordance with an input eleventh instruction, and

said timing generating means includes means, responsive to the first and second transfer instructions and the second address, for selectively generating the third conversion instruction including the ninth and eleventh instructions in the first transfer cycle and the tenth instruction in the second transfer cycle and for outputting the first conversion instruction to said bus converter means.

17. The apparatus according to claim 15, wherein said third means comprises:

ninth transfer means, coupled to said first data bus and said third data bus, for selectively inputting into said ninth transfer means the FNOD on said first data bus in accordance with an input twelfth instruction to hold the FNOD and for selectively outputting the held data onto said first data bus in accordance with an input thirteenth instruction; and

tenth transfer means, coupled to said first data bus and said third data bus, for selectively transferring the SNOD from said second data bus onto said third data bus in accordance with an input fourteenth instruction, and

said timing generating means includes means, responsive to the first and second transfer instructions and the second address, for selectively generating the third conversion instruction including the twelfth and fourteenth instructions in the first transfer cycle and the thirteenth instruction in the second transfer cycle and for outputting the first conversion instruction to said bus converter means.

18. A method of applying a 2n-bit data transfer instruction to a device having an n-bit data bus width, said method comprising the steps of:

performing a first access cycle and selectively performing a second access cycle, in accordance with the 2n-bit data transfer instruction and first and second addresses;

sequentially transferring first n-bit output data ("FNOD") and second n-bit output date ("SNOD") constituting 2n-bit output data on a first 2n-bit data bus to the device through a n-bit data bus to which the device is coupled, in the first and second access cycles, respectively; and

holding first n-bit input data ("FNID") on the n-bit data bus to output the held data to the 2n-bit data bus together with second n-bit input data ("SNID") on the n-bit data bus, as a 2n-bit input data, the FNID and the SNID being output from the device onto the n-bit data bus in the first and second access cycles, respectively, and the first and second access addresses being associated with the FNOD and SNOD or the FNID and SNID.

19. The method according to claim 18 further comprising the steps of:

holding a microprocessor, which is coupled to the 2n-bit data bus, in a wait state before the first access cycle is completed and releasing the microprocessor from the wait state before the second access cycle is completed, the microprocessor generating the 2n-bit data transfer instruction in response to an input 2n-bit data transfer command, selectively outputting the 2n-bit output data onto the 2n-bit data bus, and selectively inputting the 2n-bit input data from the 2n-bit data bus.

20. The method according to claim 19 further comprising the steps of:

latching the first access address from the microprocessor to output the latched first access address to the device and selectively updating the latched first access address between the first and second access cycles to output the updated address as the second access address to the device.