Signal recognition system
First Claim
1. A signal persistence recognition system for changing binary-valued output signals only after a change in corresponding binary-valued input signals has persisted for at least a predetermined time interval, said system comprising:
- scanning means for periodically outputting a binary-valued signal representation of the state of each specified one of a plurality of said input signals;
first memory means for storing and outputting a plurality of binary output values each representative of the state of a different specified one of said output signals;
first gating means responsive to outputs from said scanning means and said first memory means for outputting a first control signal indicating whether or not the binary-valued signal output by said scanning means for a specified one of said input signals is equivalent to the binary value output by said first memory means representative of a corresponding one of said output signals;
second memory means for storing and outputting a respective initial value representative of the duration of said predetermined time interval for each of said input signals;
third memory means for inputting, storing and outputting for each specified one of said input sginals, respective input data including a respective count value corresponding to the elapsed time since the state of said each specified input signal last changed state without any change in the corresponding output signal and a respective control bit indicative of whether said predetermined time limit has already elapsed; and
processing means responsive to the count value and the control bit output by said third memory means, to the output of said second memory means, and to said first control signal output by said first gating meansfor, when said first control signal indicates a difference between corresponding specified ones of said input and output signals, and said control bit does not indicate that the respective said predetermined interval had already elapsed,in the event said count value corresponds to an elapsed time equal to said respective predetermined time interval, setting the respective control bit stored in said third memory means and toggling the respective binary output value stored in said first memory means or,in the event said respective predetermined time interval has not yet reached, incrementing the respective sad count value without setting the respective control bit and without toggling the respective binary output value stored in said first memory means andfor, when said first control signal indicates no difference between corresponding specified ones of said input and outut signalsreplacing said respective count value stored in said third memory means with said initial value stored in said second memory means, andresetting said respective control bit.
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Abstract
A signal persistence time interval recognition system reproduces a condition of an input signal as a condition of an output signal only when the input signal condition persists for at least a predetermined time interval. The system periodically scans the input signal condition and has a first memory (ROM) for storing a start value indicative of the time interval. A second memory (RAM) stores a value indicative of the time counted since the detection of a difference between the input and output signal conditions. A third memory stores the output signal condition and a processor brings the start value from the first memory into the second memory when no difference is detected. The processor modifies the value in the second memory each time such a difference is detected and until a value is reached indicating that the time interval has been counted, the output signal condition in the third memory being then changed. The first memory only stores a single start value for all conditions of the input signal and the processor perform the modification in the second memory independently of the first memory.
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Citations
13 Claims
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1. A signal persistence recognition system for changing binary-valued output signals only after a change in corresponding binary-valued input signals has persisted for at least a predetermined time interval, said system comprising:
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scanning means for periodically outputting a binary-valued signal representation of the state of each specified one of a plurality of said input signals; first memory means for storing and outputting a plurality of binary output values each representative of the state of a different specified one of said output signals; first gating means responsive to outputs from said scanning means and said first memory means for outputting a first control signal indicating whether or not the binary-valued signal output by said scanning means for a specified one of said input signals is equivalent to the binary value output by said first memory means representative of a corresponding one of said output signals; second memory means for storing and outputting a respective initial value representative of the duration of said predetermined time interval for each of said input signals; third memory means for inputting, storing and outputting for each specified one of said input sginals, respective input data including a respective count value corresponding to the elapsed time since the state of said each specified input signal last changed state without any change in the corresponding output signal and a respective control bit indicative of whether said predetermined time limit has already elapsed; and processing means responsive to the count value and the control bit output by said third memory means, to the output of said second memory means, and to said first control signal output by said first gating means for, when said first control signal indicates a difference between corresponding specified ones of said input and output signals, and said control bit does not indicate that the respective said predetermined interval had already elapsed, in the event said count value corresponds to an elapsed time equal to said respective predetermined time interval, setting the respective control bit stored in said third memory means and toggling the respective binary output value stored in said first memory means or, in the event said respective predetermined time interval has not yet reached, incrementing the respective sad count value without setting the respective control bit and without toggling the respective binary output value stored in said first memory means and for, when said first control signal indicates no difference between corresponding specified ones of said input and outut signals replacing said respective count value stored in said third memory means with said initial value stored in said second memory means, and resetting said respective control bit. - View Dependent Claims (2, 3)
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4. A signal persistence recognition system for changing binary-valued output signals only after a change in corresponding binary-valued input signals has persisted for at least a predetermined time interval, said system comprising:
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scanning means for periodically outputting a binary-valued signal representation of the state of each specified one of a plurality of said input signals; first memory means for storing and outputting a plurality of binary output values each representative of the state of a different specified one of said output signals; first gating means responsive to outputs from said scanning means and said first memory means for outputting a first control signal indicating whether or not the binary-valued signal output by said scanning means for a specified one of said input signals is equivalent to the binary value output by said first memory means representative of a corresponding one of said output signals; second memory means for storing and outputting a respective multi-bit initial value representative of the duration of said predetermined time interval for each of said input signals; third memory means for inputting, storing and outputting for each specified one of said input signals, respective input data including a respective multi-bit count value corresponding to the elapsed time since the state of said each specified input signal last changed state without any change in the corresponding output signal and a respective control bit indicative of whether said predetermined time limit has already elapsed; and processing means responsive to the count value and the control bit output by said third memory means, to the output of said second memory means, and to said first control signal output by said first gating means for, when said first control signal indicates a difference between corresponding specified ones of said input and output signals, and said control bit does not indicate that the respective said predetermined interval had already elapsed, in the event said count value corresponds to an elapsed time equal to said respective predetermined time interval, setting the respective control bit stored in said third memory means and toggling the respective binary output value stored in said first memory means or, in the event said respective predetermined time interval has not yet been reached, incrementing the respective said count value without setting the respective control bit and without toggling the respective binary output value stored in said first memory means and for, when said first control signal indicates no difference between corresponding specified ones of said input and output signals replacing said respective count value stored in said second memory means with said initial value stored in said second memory means, and resetting said respective control bit, said processing means comprising an adder circuit having a first adder input, a second adder input, a sum output and a carry output, second gating means responsive to said first control signal and to said control bit for coupling either an output of said second memory means or an output of said third memory means to said first adder input, clock means for generating a first timing signal, and third gating means responsive to said carry output, to said first control signal and to said first timing signal for causing said adder sum output to be incremented serially relative to said first adder input if and only if said first control signal indicates that the specified input signal is different from the corresponding output signal. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification