Signal recognition system

• US 4,860,230 A
• Filed: 09/21/1987
• Issued: 08/22/1989
• Est. Priority Date: 12/22/1983
• Status: Expired due to Fees

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: Alcatel NV (Nokia Corporation)
• Inventors: Rahier, Michel C. A. R., Sallaerts, Daniel
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Dixon, Joseph L.
• Application Number:
  US07/099,706
• Time in Patent Office: 701 Days
• Field of Search: 364/569, 364/486, 379/377, 379/378, 379/382-385, 379/294, 379/255, 379/252, 379/286, 379/386, 379/283, 370/110.1, 370/110.2, 340/365 E, 371/62, 307/234, 307/265, 307/47, 377/20, 377/26, 328/58, 328/111, 328/120, 328/129.1
• US Class Current: 700/306
• CPC Class Codes: G01R 19/16557 Logic probes, i.e. circuits indicating logic state (high, low, O); modifications of electronic switches or gates for indicating state of switch H03K17/18
• CPC Class Codes: G01R 29/0273 the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)

Abstract

A signal persistence time interval recognition system reproduces a condition of an input signal as a condition of an output signal only when the input signal condition persists for at least a predetermined time interval. The system periodically scans the input signal condition and has a first memory (ROM) for storing a start value indicative of the time interval. A second memory (RAM) stores a value indicative of the time counted since the detection of a difference between the input and output signal conditions. A third memory stores the output signal condition and a processor brings the start value from the first memory into the second memory when no difference is detected. The processor modifies the value in the second memory each time such a difference is detected and until a value is reached indicating that the time interval has been counted, the output signal condition in the third memory being then changed. The first memory only stores a single start value for all conditions of the input signal and the processor perform the modification in the second memory independently of the first memory.

Claims

1. A signal persistence recognition system for changing binary-valued output signals only after a change in corresponding binary-valued input signals has persisted for at least a predetermined time interval, said system comprising:

scanning means for periodically outputting a binary-valued signal representation of the state of each specified one of a plurality of said input signals;

first memory means for storing and outputting a plurality of binary output values each representative of the state of a different specified one of said output signals;

first gating means responsive to outputs from said scanning means and said first memory means for outputting a first control signal indicating whether or not the binary-valued signal output by said scanning means for a specified one of said input signals is equivalent to the binary value output by said first memory means representative of a corresponding one of said output signals;

second memory means for storing and outputting a respective initial value representative of the duration of said predetermined time interval for each of said input signals;

third memory means for inputting, storing and outputting for each specified one of said input sginals, respective input data including a respective count value corresponding to the elapsed time since the state of said each specified input signal last changed state without any change in the corresponding output signal and a respective control bit indicative of whether said predetermined time limit has already elapsed; and

processing means responsive to the count value and the control bit output by said third memory means, to the output of said second memory means, and to said first control signal output by said first gating means

for, when said first control signal indicates a difference between corresponding specified ones of said input and output signals, and said control bit does not indicate that the respective said predetermined interval had already elapsed,

in the event said count value corresponds to an elapsed time equal to said respective predetermined time interval, setting the respective control bit stored in said third memory means and toggling the respective binary output value stored in said first memory means or,

in the event said respective predetermined time interval has not yet reached, incrementing the respective sad count value without setting the respective control bit and without toggling the respective binary output value stored in said first memory means and

for, when said first control signal indicates no difference between corresponding specified ones of said input and outut signals

replacing said respective count value stored in said third memory means with said initial value stored in said second memory means, and

resetting said respective control bit.

2. A signal persistence recognition system according to claim 1, wherein said input signals represent the respective signal states of a telecommunication line.

3. An integrated circuit chip comprising the signal persistence recognition system of claim 1.

4. A signal persistence recognition system for changing binary-valued output signals only after a change in corresponding binary-valued input signals has persisted for at least a predetermined time interval, said system comprising:

scanning means for periodically outputting a binary-valued signal representation of the state of each specified one of a plurality of said input signals;

first memory means for storing and outputting a plurality of binary output values each representative of the state of a different specified one of said output signals;

first gating means responsive to outputs from said scanning means and said first memory means for outputting a first control signal indicating whether or not the binary-valued signal output by said scanning means for a specified one of said input signals is equivalent to the binary value output by said first memory means representative of a corresponding one of said output signals;

second memory means for storing and outputting a respective multi-bit initial value representative of the duration of said predetermined time interval for each of said input signals;

third memory means for inputting, storing and outputting for each specified one of said input signals, respective input data including a respective multi-bit count value corresponding to the elapsed time since the state of said each specified input signal last changed state without any change in the corresponding output signal and a respective control bit indicative of whether said predetermined time limit has already elapsed; and

processing means responsive to the count value and the control bit output by said third memory means, to the output of said second memory means, and to said first control signal output by said first gating means

for, when said first control signal indicates a difference between corresponding specified ones of said input and output signals, and said control bit does not indicate that the respective said predetermined interval had already elapsed,

in the event said count value corresponds to an elapsed time equal to said respective predetermined time interval, setting the respective control bit stored in said third memory means and toggling the respective binary output value stored in said first memory means or,

in the event said respective predetermined time interval has not yet been reached, incrementing the respective said count value without setting the respective control bit and without toggling the respective binary output value stored in said first memory means and

for, when said first control signal indicates no difference between corresponding specified ones of said input and output signals

replacing said respective count value stored in said second memory means with said initial value stored in said second memory means, and

resetting said respective control bit,

said processing means comprising

an adder circuit having a first adder input, a second adder input, a sum output and a carry output,

second gating means responsive to said first control signal and to said control bit for coupling either an output of said second memory means or an output of said third memory means to said first adder input,

clock means for generating a first timing signal, and

third gating means responsive to said carry output, to said first control signal and to said first timing signal for causing said adder sum output to be incremented serially relative to said first adder input if and only if said first control signal indicates that the specified input signal is different from the corresponding output signal.

5. A signal persistence recognition system according to claim 4, wherein:

said first memory means comprises a first plurality of toggle flipflops for storing respective ones of said plurality of binary output values, and

said clock means generates read and write signals and a plurality of timing signals, and

said processing means further comprises;

a fourth gating means, responsive to said carry output, to a write signal and to a second timing signal generated by said clock means, for causing a corresponding one of said plurality of toggle flipflops to toggle when said adder produces an overflow condition.

6. A signal persistence recognition system according to claim 5 wherein

said scanning means further comprises

a first multiplexer, to the respective inputs of which said input signals are applied, and

said first memory means further comprises

a second multiplexer whose respective inputs are coupled to the corresponding outputs of said plurality of flipflops,

the outputs of said first and second multiplexers being coupled to respective inputs of said first gating means.

7. A signal persistence recognition system according to claim 6, wherein

said clock means includes a timing circuit which generates a plurality of successive time interval signals, allocated to respective ones of said input signals, for controlling said first and second multiplexers, said timing circuit generating for each such time interval signal a series of successive bit period signals successively allocated to respective ones of said bits of said multi-bit count value and to said control bit.

8. A signal persistence recognition system according to claim 7, said adder circuit is a 1-bit adder able to add a 0 or a 1 to the initial or count values respectively stored in said second and said third memory means, and that said first and second timing signals are the first and penultimate bit period signals of said series of said first bit period signals and are respectively allocated to the first and last bits of said count value stored in said third memory means, and that the last bit period signal of said series of said bit period signals is allocated to said control bit.

9. A signal persistence recognition system according to claim 8, wherein during said last bit period signal a 0 is applied to said first adder input.

10. A signal persistence recognition system according to claim 4 wherein said first gating means comprises an exclusive or gate and a bistate device, the output of said exclusive or gate being coupled to an input of said bistate device for providing said first contrl signal.

11. A signal persistence recognition system according to claim 5, wherein each of said toggle flipflops includes a first and a second loop, said first loop comprising the cascade connection of a first switch, a first inverter, a second inverter, a third switch and a third inverter, whilst said second loop comprises the cascade connection of said first and second inverters and of a fourth switch, the junction point of said first and second inverters constituting the output of said each toggle flipflop, said first switch being controlled by a respective one of said time interval signals, said second switch being controlled by an output signal of said fourth gating means and said third and fourth switches being controlled by said read signal.

12. A signal persistence recognition system according to claim 11, wherein

said bistate device is a master/slave flipflop including a slave loop and a master loop, said slave loop comprising the cascade connection of a fourth and a fifth inverter and a fifth switch and said master loop comprising the cascade connection of a sixth and a seventh inverter and a sixth switch, and

a data input of said master/slave flipflop is connected to the output thereof via the cascade connection of a seventh switch, said fourth and fifth inverters, an eighth switch and said sixth and seventh inverters, said sixth and seventh switches being controlled by a second control signal which is deactivated for substantially said last and first bit period signals and said fifth and eighth switches being controlled by a third control signal which is activated from the end of said last bit period signal for substantially one such time period.

13. A signal persistence recognition system according to claim 12, wherein

each memory cell of said third memory means includes a loop comprising the cascade connection of eighth and ninth inverters and a ninth switch, said cell having a data input and a data output which are connected via the cascade connection of tenth and eleventh switches, said eighth and ninth inverters and a twelfth switch and

said eleventh and twelfth switches are controlled by a corresponding time interval signal, said ninth switch is controlled by said read signal of each bit period signal and said twelfth switch is controlled by said write signal.