High speed cellular processing system

• US 4,860,375 A
• Filed: 03/10/1986
• Issued: 08/22/1989
• Est. Priority Date: 03/10/1986
• Status: Expired due to Fees

• Current Assignee: Environmental Research Institute Incorporated
• Original Assignee: Environmental Research Institute of Michigan
• Inventors: Lougheed, Robert M., McCubbrey, David L.
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Mancuso, Joseph
• Application Number:
  US06/837,770
• Time in Patent Office: 1,261 Days
• Field of Search: 382/41, 382/27, 382/49, 364/736, 364/715, 364/133, 364/140
• US Class Current: 382/303
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A cellular processing system for analyzing an image comprising a matrix of points employs an image memory for storing digital data signals representative of each of the points, a plurality of special function processing units, each adapted to perform a specific operation on one or more images, and data bus means for selectively distributing image data from the image memory to one or more preselected function processors for processing in a cascaded fashion and returning the processed data signals back to image memory. The special function process units include a pipeline processor employing one or more programmable, substantially identical neighborhood transformation stages and an image combiner including means for performing arithmetic, logical, and conditional operations on one or more images.

Claims

1. A cellular data processing system for analyzing one or more images each comprising a matrix of points, each point being represented by digital image data, said system comprising:

an image memory for storing an array of digital image data corresponding to at least one image;

a pipeline processor including at least one substantially identical neighborhood transformation stages, each neighborhood transformation stage having means for receiving a serial stream of digital image data corresponding to a raster scan of a matrix of points of a selected first input image and producing a serial stream of digital image data corresponding to a raster scan of the matrix of points of a transformed image, each point in said transformed image corresponding to said digital image data of a corresponding point of said selected first input image and a predetermined plurality of points of said selected first input image in the neighborhood of said corresponding point of said selected first input image;

an image combiner connected to said pipeline processor for performing a selected one of a predetermined set of arithmetic, logical and conditional operations for combining a serial stream of digital image data of a second selected input image with corresponding digital image data of said transformed image thereby forming a serial stream of digital image data corresponding to a combined image;

a source data bus connected to said image memory, said pipeline processor and said image combiner for supplying said serial stream of digital image data corresponding to said selected first input image from said image memory to said pipeline processor and said serial stream of digital image data corresponding to said selected second input image from said image memory to said image combiner; and

a destination data bus connected to said image memory and said image combiner for supplying said serial stream of digital image data corresponding to said combined input image from said image combiner to said image memory for storage therein.

2. A cellular processing system according to claim 1 wherein the image memory includes:

a memory array for storing digital image data;

a read region control means for accessing the digital image data in a predefined sub-image region of said memory array, the predefined sub-image region occupying less than the entire portion of said memory array;

a means for outputting the digital iamge data in the predefined sub-image region as a serial stream to said source data bus for distributing digital image data to one or more of said pipeline processor and said image combiner.

3. The cellular processing system according to claim 2 wherein said read region control means in a programmable address generator.

4. A cellular processing system of claim 3 including control means for accessing preselected subimage regions of the image memory array on each of a plurality of circuit boards in a predetermined sequence to obtain a single image.

5. The cellular processing system of claim 4 wherein said read region control means includes a programmable address generator and a programmable delayed start register located on each of said plural circuit boards, whereby said programmable delayed start register on a particular circuit board can be programmed to delay the operation of the programmable address generator a predetermined amount of time.

6. A cellular image processing system according to claim 1 wherein the image memory includes:

a memory array for storing digital image data;

a write region control means for accessing a predefined sub-image region in said memory array, the predefined sub-image region occupying less than the entire portion of said memory array; and

an input means for placing a serial stream of digital signals received from said image combiner in the predefined sub-image region.

7. The cellular processing system according to claim 6 wherein said write region control means is a programmable address generator.

8. A cellular processing system according to claim 1 wherein said image memory is contained on one or more circuit boards.

9. The cellular processing system according to claim 1 wherein said image combiner includes:

a first calculation unit for performing arithmetic and logical operations on a pair of digital image data operands;

a second calculation unit for performing arithmetic and logical operations upon a pair of digital image data operands; and

a conditional logic unit operable to enable said second calculation unit to perform one of a plurality of alternative operations upon the pair of digital image data operands in said second calculation unit, said selected operation being a function of the output from said first calculation unit.

10. The cellular processing system of claim 9 wherein each of said first and second calculation units includes means for selectively disabling the processing of particular bits in said digital image data operands by said calculation unit such that the particular bits pass unmodified in value through said calculation unit.

11. A cellular data processing system for analyzing images wherein each image is made up of a matrix of points, each point being represented by digital image data, the system including:

a image memory for storing said digital image data representing the image points;

a neighborhood processing pipeline including a chain of a plurality of substantially identical neighborhood transformation stages, each stage adapted to perform a transformation selected from a predetermined set of transformations on a serial stream of digital image data representing a complete image, thereby forming a serial stream of digital image data representing a transformed image, said neighborhood transformation stages disposed in cascade to receive said serial stream of digital image data from a prior neighborhood transform stage;

a pipeline port including -

means for programming each of the neighborhood transformation stages for performing a particular transformation on said digital image data,

means for receiving a serial stream of digital image data representing an image from the image memory, and

means for routing said serial stream of digital image data to the first stage neighborhood transformation stage of said neighborhood processing pipeline;

an image combiner including means for performing arithmetic, logical and conditional operations on serial streams of digital image data corresponding to a pair of images;

a first data bus means for routing digital image data corresponding to a first image from said image memory to said pipeline port;

a second data bus means for routing digital image data corresponding to a second image from said image memory to said image combiner;

a third data bus means for routing digital image data from the last of said neighborhood transformation stages, output by the neighborhood processing pipeline, to said image combiner; and

a fourth data bus means for routing digital image data corresponding to a third image resulting from the output of said image combiner to said image memory.

12. The cellular data processing system of claim 11 wherein said pipeline port includes means for loading program data necessary for reprogramming one or more of said neighborhood transformation stages for a following image processing cycle concurrent with processing by said neighborhood transformation stages in a current image processing cycle.

13. A cellular processing system for analyzing an image comprising a matrix of points, each point being represented by digital image data , said system including:

an image memory for storing said digital image data representing a plurality of images;

a neighborhood pipeline processor adapted to receive a serial stream of digital image data, each data image data representing a point in a particular image, said neighborhood pipeline processor including means for transforming each of said digital image data into a new value as a function of the value of certain preselected neighboring points;

a first data bus means for routing digital image data corresponding to a first image from said image memory to said neighborhood pipeline processor;

an image combiner for performing arithmetic, logical, and conditional operations on a pair of images, the first of the pair of images being represented by a serial stream of digital image data received from the output of said neighborhood pipeline processor, and the second of the pair of images being represented by a serial stream of digital image data supplied from said image memory;

a second data bus means for routing image data corresponding to said second image from said image memory to said image combiner;

a third data bus means for routing the image data corresponding to said transformed first image from the output of said neighborhood pipeline processor to said image combiner; and

a control means for delaying the routing of the digital image data representing said second image for a preselected interval of time to insure that the image data from said first image and said second image are received simultaneously at said image combiner.