Switched capacitor filter

• US 4,862,121 A
• Filed: 08/13/1987
• Issued: 08/29/1989
• Est. Priority Date: 08/13/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hochschild, James R., Severin, William A.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Lee, Benny
• Application Number:
  US07/085,054
• Time in Patent Office: 747 Days
• Field of Search: 333/173, 333/214, 333/216, 333/19, 330/51, 330/107, 330/109
• US Class Current: 333/173
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

A biquadrature switched capacitor filter having differential input/output integrator amplifiers (12,34) and switched capacitor networks (16,28,36,40). The differential outputs of one amplifier (12) are crossed and connected to the switched capacitor networks (36,40) of the other amplifier (34) to provide a negative capacitance effect. Feedforward capacitors (70,72) are switched to prevent the stage input signals (IN+, IN-) from being coupled during certain phases of a biphase nonoverlapping clock. In high-pass applications, a feedback capacitor (134, 136) makes positioning of pole and zero responses easy. Amplifier bandwidth is controlled by switched capacitors (148, 152) connected to the amplifiers during certain clock phases.

Claims

1. A switched capacitor filter, comprising:

a pair of series-connected integrators each having at least one input terminal, one of said input terminals having a switched capacitor input network connected thereto;

a feedforward switched capacitor circuit for coupling a signal from an input of one said integrator input network to an input terminal of the other integrator; and

a nonoverlapping biphase clock for driving said switched capacitor input networks during one phase for sampling an input signal and during another phase for settling of said filter, said clock being connected to said switched capacitor networks for causing said integrators to simultaneously sample and simultaneously settle toward a steady state value during said respective different clock phases, said clock being connected to said feedforward switched capacitor circuit to switch in said feedforward capacitor during said one phase and switch out said feedforward capacitor during said other phase, wherein said integrators each comprise a differential input/output integrator amplifier.

2. The switched capacitor filter of claim 1, wherein said feedforward switched capacitor circuit is connected to said one clock phase to allow a signal to be coupled through said switched capacitor networks.

3. The switched capacitor filter of claim 1, further including a capacitor connected to said feedforward switched capacitor circuit and to an output of one said integrator to provide a desired high-pass characteristic to said filter.

4. The switched capacitor filter of claim 1, further including one said switched capacitor input network connected to each input terminal of each said integrator amplifier.

5. The switched capacitor filter of claim 4, wherein each said switched capacitor input network comprises a pair of transistor switches connected in series with a capacitor, and a pair of transistor switches connected to shunt both sides of said capacitor to ground.

6. The switched capacitor filter of claim 5, wherein said series transistor switches are driven by one said clock phase and said shunt transistor switches are driven by another said clock phase.

7. The switched capacitor filter of claim 6, wherein substantially identical said switched capacitor networks are connected to each differential input of each said integrator amplifier.

8. The switched capacitor filter of claim 1, wherein one said differential integrator amplifier is connected to a switched capacitor input network of said other integrator differential amplifier in a manner as to produce a negative capacitance effect.

9. A switched capacitor filter, comprising:

a pair of series-connected integrators each having at least one input terminal, one of said input terminals having a switched capacitor input network connected thereto;

a feedforward switched capacitor circuit for coupling a signal form an input of one said integrator input network to an input terminal of the other integrator; and

a nonoverlapping biphase clock for driving said switched capacitor input network during one phase for sampling an input signal and during another phase for settling of said filter, said clock being connected to said switched capacitor networks for causing said integrators to simultaneously sample and simultaneously settle toward a steady state value during said respective different clock phases, said clock being connected to said feedforward switched capacitor circuit to switch in said feedforward capacitor during said one phase and switch out said feedforward capacitor during said another phase,

said integrators each comprising a differential input/output integrator amplifier,

each said differential amplifier including a differential output comprising an inverting and a noninverting output, said inverting output of one said integrator amplifier driving the switched capacitor input network associated with an inverting input of said another integrator amplifier, and wherein the noninverting differential output of one said integrator amplifier drives a switched capacitor input network associated with a noninverting input of said another integrator amplifier.

10. A method for fabricating a switched capacitor filter, comprising the steps of:

connecting in series a pair of integrators having at least one input terminal, one of said input terminals having a switched capacitor input network connected thereto;

connecting a feedforward switched capacitor circuit for coupling a signal from an input of one said integrator input network to an input terminal of the other integrator;

connecting a nonoverlapping biphase clock to said filter for driving said switched capacitor input networks during one phase for sampling an input signal and during another phase for settling of said filter, said clock being connected to said switched capacitor networks for causing said integrators to simultaneously sample and simultaneously settle toward a steady state value during said respective different clock phases, said clock being connected to said feedforward switched capacitor circuit to switch in said feedforward capacitor during said one phase and switch out said feedforward capacitor during said other phase; and

connecting said integrators together using switched capacitor networks to achieve a negative capacitance,

each said integrator includes a differential amplifier with a differential output comprising an inverting and a noninverting output, and further including connecting said inverting output of one said integrator amplifier so as to drive a switched capacitor input network associated with an inverting input of said other integrator amplifier, and connecting the noninverting differential output of one said integrator amplifier so as to drive a switched capacitor input network associated with a noninverting input of said other integrator amplifier.

11. A method for fabricating a switched capacitor filter network comprising:

a plurality of individual filters connected together to provide an overall filter function, each said individual filter formed by the steps of,

connecting in series a pair of integrators having at least one input terminal, one of said input terminals having a switched capacitor input network connected thereto;

connecting a feedforward switched capacitor circuit for coupling a signal from an input of one said integrator input network to an input terminal of the other integrator;

connecting a nonoverlapping biphase clock to said filter for driving said switched capacitor input networks during one phase for sampling an input signal and during another phase for settling of said filter, said clock being connected to said switched capacitor networks for causing said integrators to simultaneously sample and simultaneously settle toward a steady state value during said respective different clock phases, said clock being connected to said feedforward switched capacitor circuit to switch in said feedforward capacitor during said one phase and switch out said feedforward capacitor during said another phase; and

connecting said filter to an analog interface circuit for processing input analog signals to said switched capacitor network to provide output digital signals.

12. A switched capacitor filter, comprising:

a pair of series-connected integrators each having at least one input terminal, one of said input terminals having a switched capacitor input network connected thereto;

a feedforward switched capacitor circuit for coupling a signal from an input of one said integrator input network to an input terminal of the other integrator;

a nonoverlapping biphase clock for driving said switched capacitor input networks during one phase for sampling an input signal and during another phase for settling of said filter, said clock being connected to said switched capacitor networks for causing said integrators to simultaneously sample and simultaneously settle toward a steady state value during said respective different clock phases, said clock being connected to said feedforward switched capacitor circuit to switch in said feedforward capacitor during said one phase and switch out said feedforward capacitor during said other phase; and

a capacitive load connected to the output of at least one said integrator for reducing the bandwidth thereof.

13. The switched capacitor filter of claim 12, wherein said loading capacitor is switched with a transistor switch during one phase of said clock.

14. The switched capacitor filter of claim 12, wherein said integrators each include an amplifier, and wherein at least one of said capacitive load is a fixed capacitor connected to said one amplifier output for providing a capacitive loading thereto during both said clock phases, and further including a switched capacitor connected to at least one said amplifier output for providing an additional load thereto during one said clock phase.

15. A switched capacitor filter, comprising:

a pair of series-connected integrator amplifiers having first input terminals, each first input terminal having a switched capacitor input network connected thereto;

a feedforward switched capacitor circuit for coupling a signal from an input of one said integrator input network to an input terminal of said another said integrator;

a feedwork capacitor connected between an output of one said amplifier and an input of said another said amplifier for providing a composite signal having components of said amplifier output and of said feedforward switched capacitor circuit to provide an effective summation thereof provided to the input of said another amplifier; and

a nonoverlapping biphase clock for driving said switched capacitor input networks during one phase for sampling and during another phase for settling of said filter, said clock being connected to said switched capacitor networks for causing said integrator amplifiers to simultaneously sample and simultaneously settle toward a steady state value during said respective different clock phases, said clock being connected to said feedforward switched capacitor circuit to switch in said feedforward capacitor during said one phase and switch out said feedforward capacitor during the other phase, wherein said filter comprises a high-pass filter, and a capacitance value of said feedforward capacitor establishes a pole-zero position of a transfer function characteristic of said filter.

16. A switched capacitor filter network comprising:

a plurality of switched capacitor filters connected together to provide an overall filter function, each filter including,

a pair of series-connected integrators each having at least one input terminal, one of said input terminals having a switched capacitor input network connected thereto;

a feedforward switched capacitor circuit for coupling a signal from an input of one said integrator input network to an input terminal of the other integrator; and

a nonoverlapping biphase clock for driving said switched capacitor input networks during one phase for sampling an input signal and during another phase for settling of said filter, said clock being connected to said switched capacitor networks for causing said integrators to simultaneously sample and simultaneously settle toward a steady state value during said respective different clock phases, said clock being connected to said feedforward switched capacitor circuit to switch in said feedforward capacitor during said one phase and switch out said feedforward capacitor during said other phase; and

analog interface circuits for processing input analog signals to said switch capacitor network to provide output digital signals.

17. The switched capacitor filter of claim 16, wherein at least one of said switched capacitor filters operates to provide an equalization function, and at least one of said switched capacitor filters operates for providing a high-pass function.

18. A method for fabricating a switched capacitor filter, comprising the steps of:

connecting in series a pair of integrators having at least one input terminal, one of said input terminals having a switched capacitor input network connected thereto;

connecting a feedforward switched capacitor circuit for coupling a signal from an input of one said integrator input network to an input terminal of the other integrator;

connecting a nonoverlapping biphase clock to said filter for driving said switched capacitor input networks during one phase for sampling an input signal and during another phase for settling of said filter, said clock being connected to said switched capacitor networks for causing said integrators to simultaneously sample and simultaneously settle toward a steady state value during said respective different clock phases, said clock being connected to said feedforward switched capacitor circuit to switch in said feedforward capacitor during said one phase and switch out said feedforward capacitor during said another phase; and

connecting a capacitive load to the output of at least one said integrator for reducing the bandwidth thereof.

19. The method of claim 18, further including switching said load capacitor with a transistor switch during one phase of said clock.

20. The method of claim 18, wherein said integrators each include an amplifier, and further including fixing a capacitor to said one amplifier output for providing a capacitive loading thereto during both said clock phases, and switching capacitor for providing an additional load thereto during one said clock phase.

21. A biquadratic switched capacitor filter, comprising:

a pair of differential input/output amplifiers, and having respective capacitors connected thereto to provide integrator functions with respect to each said amplifier;

a switched capacitor network connected to each differential input of each said amplifier, each said switched capacitor network comprising a pair of transistor switches connected in series with a capacitor, and a pair of transistor switches connected to said capacitor for grounding said capacitor;

a biphase nonoverlapping clock, one phase thereof for driving said series transistor switches of each said switched capacitor network, and the other phase thereof for driving said transistor switches for grounding said capacitor; and

a pair of switched feedforward capacitors, each connected between a differential input of one said integrator amplifier and a differential input of the other said integrator amplifier, said switched feedforward capacitor comprising a capacitor connected in series with a transistor switch, said switch being driven by the clock phase which also drives said series-connected transistor switches of said switched capacitor networks.

22. The switched capacitor filter of claim 21, further including means for balancing a capacitive load of at least one said integrator amplifier connected thereto during said clock phases.

23. The biquadratic switched capacitor filter of claim 21, wherein said filter is fabricated in integrated circuit form having analog circuits and digital circuits.

24. A method for controlling the bandwidth of amplifiers employed in a switched capacitor filter, said amplifiers having output terminals, comprising the steps of:

switchably connecting a capacitor between output terminals of said amplifier such that in one switch position said capacitor adds a desired capacitive loading to said amplifier to reduce the bandwidth and connected such that in another switch position said capacitor load is removed without said capacitor being discharged to ground; and

switching said capacitor during one phase of a biphase clock so as to provide additional capacitive loading to said amplifier during said switched phase and thereby reduce the bandwidth thereof.

25. The method of claim 24, further including connecting a fixed capacitor to said amplifier output terminals.

26. The method of claim 24, wherein said amplifier has differential outputs and further including switching said capacitor so as to provide a capacitive loading between said differential outputs of said amplifier.

27. The method of claim 24, further including connecting said capacitor having about half said desired value to said amplifier output, and switchably connecting another substantially similar valued capacitor to said amplifier output and switching said similar valued capacitor in phase with the switching of said capacitor.