Scalable fuse link element

• US 4,862,243 A
• Filed: 06/01/1987
• Issued: 08/29/1989
• Est. Priority Date: 06/01/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Welch, Michael T., Torreno, Manuel L. Jr., Garcia, Evaristo Jr., McMann, Ronald E.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/057,064
• Time in Patent Office: 820 Days
• Field of Search: 357/51
• US Class Current: 257/529
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Claims

1. A semiconductor device comprising:

a semiconductor surface having an active device;

two electrically conducting interconnects spaced over said semiconductor surface;

a fuse layer formed between said semiconductor surface and said interconnects, said fuse layer having a linking portion of a predetermined shape between said interconnects; and

an isolating layer formed over said linking portion, said isolating layer also having said predetermined shape of said fuse layer, said interconnects have an edge extending over a portion of said isolating layer, said fuse layer being electrically isolated from desired portions of said semiconductor surface.

2. The semiconductor device of claim 1 and further comprising a barrier layer formed between said interconnects and said semiconductor surface.

3. A semiconductor device of claim 1 wherein said interconnects comprise first layer interconnects and further comprising a second level interconnect electrically connected to one of said first level interconnects.