Packaging system for stacking integrated circuits

• US 4,862,249 A
• Filed: 04/17/1987
• Issued: 08/29/1989
• Est. Priority Date: 04/17/1987
• Status: Expired due to Fees

• Current Assignee: XOC Devices Incorporated
• Original Assignee: XOC Devices Incorporated
• Inventors: Carlson, Randolph S.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Clark, Sheila V.
• Application Number:
  US07/039,632
• Time in Patent Office: 865 Days
• Field of Search: 357/80, 357/75, 357/74, 357/70, 357/68, 357/56, 357/72, 174/52 FP
• US Class Current: 257/668
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/32 Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

Integrated circuit dies are mounted to the interconnection leads on frames of tape automatic bonding (TAB) film. Thereafter, each frame of the TAB film with the attached integrated circuit die is affixed to an electrically insulating, thermally conductive plate to form a sandwich structure. A number of sandwich structures are bonded together to form a stack of the sandwiches. The interconnection leads of each sandwich in the stack are selectively electrically connected to the interconnection leads of other sandwiches in the stack to form a system of electrically interconnected integrated circuits. The system is compact and has short interconnection paths between integrated circuits so that the propagation delays of signals between integrated circuits are minimized.

Claims

1. An apparatus for interconnecting a plurality of integrated circuits in a stack, comprising:

a plurality of sandwiched structures, each sandwiched structure comprising;

an integrated circuit die having a plurality of bonding pads on an active surface thereof, said active surface of said integrated circuit die having an outer periphery;

a first set of electrical conductors, said first set of electrical conductors electrically and mechanically bonded to said bonding pads of said integrated circuit die; and

a first electrically insulating plate attached to said integrated circuit die, said first electrically insulating plate having a planar surface and an edge, said edge forming an outer periphery of said first electrically insulating plate with dimensions selected so that said outer periphery of said first electrically insulating plate extends beyond the outer periphery of said surface of said integrated circuit die and so that an exposed portion of a plurality of conductors of said first set of electrical conductors extends to the outer periphery of said first electrically insulating plate, said plurality of sandwiched structures positioned with respect to each other in said stack so that said planar surfaces of said first insulating plates are substantially parallel, with at least one edge of each of said first insulating plates aligned to form a common outer surface of said stack, said plurality of sandwiched structures further oriented so that the active surfaces of the integrated circuit dies in at least two of said sandwiched structures face in the same direction; and

a second set of electrical conductors formed on said common outer surface of said stack that electrically interconnects exposed portions of a plurality of conductors of said first set of electrical conductors of one of said sandwiched structures with exposed portions of a plurality of conductors of said first set of electrical conductors of others of said sandwiched structures.

2. The apparatus as defined in claim 1, wherein said first electrically insulating plate comprises sapphire.

3. The apparatus as defined in claim 2, wherein said first electrically insulating plate is circular.

4. The apparatus as defined in claim 1, wherein at least one of said sandwiched structures further includes a second electrically insulating plate having a centrally disposed cavity therein, said second electrically insulating plate positioned on said first set of electrical conductors so that said first set of electrical conductors are positioned between said second electrically insulating plate and said first electrically insulating plate.

5. The apparatus as defined in claim 4, wherein said integrated circuit die is positioned within said centrally disposed cavity of said second electrically insulating plate.

6. The apparatus as defined in claim 5, wherein said first and second electrically insulating plates comprise sapphire.

7. The apparatus as defined in claim 5, wherein said first and second electrically insulating plates are thermally conductive.

8. The apparatus as defined in claim 4, wherein said first and second electrically insulating plates are circular.

9. The apparatus as defined in claim 1, wherein said first plurality of electrical conductors of each sandwiched structure are formed as a pattern on a frame of tape automatic bonding (TAB) film.

10. The apparatus as defined in claim 9, wherein each said frame of TAB film includes a plurality of sprocket holes and wherein said plurality of sprocket holes align said plurality of sandwiched structures when said sandwiched structures are being stacked.

11. The apparatus as defined in claim 10, wherein said plurality of sandwiched structures are bonded together with an adhesive, and wherein said sprocket holes align said plurality of sandwiched structures until said adhesive is cured.

12. The apparatus as defined in claim 9, wherein said frame of TAB film includes a plurality of sprocket holes aligned with said pattern of said first set of electrical conductors, and wherein said first electrically insulating plate is aligned with said sprocket holes so that said first electrically insulating plate is aligned with said first set of electrical conductors.

13. The apparatus as defined in claim 1, wherein said second set of electrical conductors that interconnect the exposed portions of said first sets of electrical conductors of said sandwiched structures comprises a layer of metal having portions of said metal removed to form said second set of electrical conductors.

14. An apparatus for packaging integrated circuits, comprising:

an integrated circuit die having a plurality of bonding pads on a first die surface thereof;

a plurality of electrical conductors electrically bonded to said bonding pads of said integrated circuit die, said plurality of electrical conductors comprising the electrical conductors of a frame of tape automated bonding (TAB) tape; and

a plate of thermally conductive, electrically insulating material having a first plate surface and a second plate surface, each said surface having an outer periphery, said outer periphery of each said surface encompassing an area greater than the size of said integrated circuit die so that said integrated circuit die does not extend to said outer periphery, said first plate surface positioned proximate to said first die surface of said integrated circuit die so that said plurality of electrical conductors are disposed between said first die surface and said plate, said plurality of electrical conductors having lengths selected so that said plurality of electrical conductors extend to said outer periphery of said first plate surface with at least a portion of each of said electrical conductors exposed at said outer periphery of said first plate surface, said plate adhesively bonded to said first die surface and said electrical conductors.

15. The apparatus as defined in claim 14, wherein said plate of thermally conductive, electrically insulating material comprises sapphire.

16. The apparatus as defined in claim 14, wherein said first plate surface is bonded to said first die surface.

17. The apparatus as defined in claim 14, wherein said first plate surface has a raised central portion and an outer peripheral portion, said raised central portion bonded to said first die surface, said outer peripheral portion proximate to but spaced apart from said plurality of electrical conductors.

18. The apparatus as defined in claim 14, wherein:

said integrated circuit die has a second die surface opposite said first die surface; and

said second die surface is positioned to be substantially parallel to said second plate surface.

19. The apparatus as defined in claim 18, wherein said second die surface is positioned to be substantially parallel to said second plate surface by grinding said second die surface.

20. The apparatus as defined in claim 14, further including a second thermally conductive, electrically insulating plate, said second plate having a cavity formed therein, said second plate positioned proximate to said first plate so that said plurality of electrical conductors is clamped between said first plate and said second plate and so that said integrated circuit die is positioned within said cavity of said second plate.

21. The apparatus as defined in claim 20, wherein said first and second thermally conductive, electrically insulating plates comprise sapphire.

22. The apparatus as defined in claim 20, wherein said first and second plates are circular.

23. The apparatus as defined in claim 20, wherein said second plate has first and second substantially parallel surfaces, said first surface of said second plate positioned in juxtaposition with said first surface of said first plate with said plurality of conductors therebetween, said second surface of said second plate positioned to be substantially parallel to said second surface of said first plate.

24. The apparatus as defined in claim 14, wherein said frame of TAB film has a plurality of sprocket holes that provide alignment of said conductors with said bonding pads on said first die surface and alignment of said conductors with said first plate.

25. An apparatus for interconnecting a plurality of electrical circuits in a stack, comprising:

a plurality of sandwiched structures, each sandwiched structure comprising;

an electrical circuit having a plurality of electrical interconnections on at least a first surface of a substrate, said electrical circuit constrained to an area having an outer periphery;

a first set of electrical conductors, said first set of electrical conductors electrically connected to said electrical circuit on said first surface of said substrate; and

a first electrically insulating plate adhesively bonded to said electrical circuit, said first electrical insulating plate having a planar surface and an edge, said edge forming an outer periphery of said first insulating plate with dimensions selected so that said outer periphery of said first electrically insulating plate extends beyond the outer periphery of said area in which said electrical circuit is located, and so that exposed portions of a plurality of conductors of said first set of electrical conductors extends beyond the outer periphery of said first electrically insulating plate, said plurality of sandwiched structures positioned with respect to each other in said stack so that said planar surfaces of said first insulating plates are substantially parallel, with at least one edge of each of said first insulating plates aligned to form a common outer surface of said stack, said plurality of sandwiched structures further oriented so that the first surfaces of the substrates of at least two of said sandwiched structures face in the same direction; and

a second set of electrical conductors formed on said common outer surface of said stack that electrically interconnect the exposed portions of a plurality of conductors of said first set of electrical conductors of one of said sandwiched structures with the exposed portions of a plurality of conductors of said first set of electrical conductors of others of said sandwiched structures.

26. The apparatus as defined in claim 25, wherein said electrical circuit comprises an integrated circuit die.

27. An apparatus for interconnecting a plurality of integrated circuit dies in a stack to provide short electrical interconnection paths between the dies, comprising:

a first layer comprising;

a first insulating mounting surface having a peripheral edge;

a first integrated circuit die fastened to said first insulating mounting surface, said first integrated circuit die having a plurality of bonding pads on a bonding surface thereof, said bonding surface of said first integrated circuit die being substantially parallel to said first insulating mounting surface, said bonding pads providing connections for signals to and from said first integrated circuit die; and

a first set of interconnection leads connected to said bonding pads and extending to said peripheral edge of said first insulating mounting surface;

a second layer comprising;

a second insulating mounting surface having a peripheral edge, said second insulating mounting surface being substantially parallel to said first insulating mounting surface, at least a portion of said peripheral edge of said second insulating mounting surface conforming in shape with, and positioned adjacent to a corresponding portion of said peripheral edge of said first insulating mounting surface to form a common outer surface of said stack;

a second integrated circuit die fastened to said second insulating mounting surface, said second integrated circuit die having a plurality of bonding pads on a bonding surface thereof, said bonding surface of said second integrated circuit die facing in the same direction as said bonding surface of said first integrated circuit die, said bonding pads providing connections for signals to and from said second integrated circuit die; and

a second set of interconnection leads connected to said bonding pads and extending to said portion of said peripheral edge of said second insulating mounting surface; and

interconnections formed on said common outer surface of said stack to provide electrical interconnections between bonding pads positioned in like locations on said bonding surface of said first and second integrated circuit dies.

28. The apparatus as defined in claim 27, wherein at least one of said interconnections between a first bonding pad on said bonding surface of said first integrated circuit die and a second bonding pad positioned in a like location on said bonding surface of said second integrated circuit die comprises only:

(a) a first interconnection from said first bonding pad to the peripheral edge of said first insulating surface, (b) a second interconnection from said second bonding pad to the peripheral edge of said second insulating surface, and (c) a third interconnection from said first interconnection to said second interconnection along said common outer surface of said stack formed by said corresponding portions of said peripheral edges of said first and second insulating mounting surfaces.

29. An apparatus for interconnecting a plurality of integrated circuit dies in a stack to provide short electrical interconnection paths between the dies, comprising:

a first layer comprising;

a first insulating mounting surface having an outer perimeter, at least a portion of said outer perimeter of said first insulating mounting surface forming a first portion of a side of said stack;

a first integrated circuit die fastened to said first insulating mounting surface, said first integrated circuit die having a plurality of bonding pads on a bonding surface thereof, said bonding surface of said first integrated circuit die being substantially parallel to said first insulating mounting surface, said bonding pads providing connections for signals to and from said first integrated circuit die; and

a first set of interconnection leads connected to said bonding pads and extending to said outer perimeter of said first insulating mounting surface;

a second layer comprising;

a second insulating mounting surface having an outer perimeter, said second insulating mounting surface being substantially parallel to said first insulating mounting surface, at least a portion of said outer perimeter of said second insulating mounting surface forming a second portion of said side of said stack;

a second integrated circuit die fastened to said second insulating mounting surface, said second integrated circuit die having a plurality of bonding pads on a bonding surface thereof, said bonding surface of said second integrated circuit die facing in the same direction as said bonding surface of said first integrated circuit die, said bonding pads providing connections for signals to and from said second integrated circuit die, and

a second set of interconnection leads connected to said bonding pads and extending to said outer perimeter of said second insulating mounting surface; and

plural connections on said side stack between said first and second sets of interconnection leads of said first and second layers, said plural connections being shorter than said interconnection leads of said first and second sets of interconnection leads.