Circuit for processing a digital signal having a blanking interval

• US 4,862,270 A
• Filed: 09/26/1988
• Issued: 08/29/1989
• Est. Priority Date: 09/29/1987
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nishio, Naoki
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Parker, Michael D.
• Application Number:
  US07/249,293
• Time in Patent Office: 337 Days
• Field of Search: 358/32, 358/142, 358/147, 358/160, 358/162, 358/164
• US Class Current: 348/721
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/20 Circuitry for controlling amplitude response
• CPC Class Codes: H04N 5/202 Gamma control circuits for controlling camera response irrespective of the scene brightness H04N23/82
• CPC Class Codes: H04N 5/208 for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction

Abstract

A digital signal processing circuit for carrying out a series of processings for a digital signal having a signal effective interval and blanking interval such as a video signal. Operation control data added to the blanking interval of the input digital signal controls the signal processings of a plurality of signal processing blocks, so that the circuit construction can be simplified and complicated signal processings can be achieved.

Claims

1. A digital signal processing circuit used in a video camera for processing a digital video signal having an effective signal interval and a blanking interval in a repeated fashion, said digital signal processing circuit comprising:

an input terminal for receiving the digital video signal;

control data generating means for generating control data with a block address;

control data inserting means for inserting said control data with the block address into the blanking interval of said digital video signal; and

a plurality of signal processing circuit blocks connected in series with each other,

each of said signal processing circuit blocks processing the effective signal interval of the digital video signal in accordance with the control data having the block address designating that block and each of said signal processing blocks including control data separating means for separating the control data having the block address designating that block.

2. a digital signal processing circuit according to claim 1, wherein each of said signal processing circuit blocks further includes an operating circuit supplied with the digital video signal and for processing the effective signal interval of the digital video signal in accordance with the control data and for supplying the processed signal to the following block.

3. A digital signal processing circuit according to claim 2, wherein each of said processing circuit blocks includes a control circuit for decoding the block address and for controlling said separating means such that the control data having the block address designating that block are separated and the control data having the block address designating another block are supplied to the following block.

4. A digital signal processing circuit according to claim 2, wherein said operating circuit of one of said signal processing blocks includes a gamma correction circuit for controlling input-output characteristics of the digital video signal and said control data control the input-output characteristics.

5. A digital signal processing circuit according to claim 4, wherein said gamma correction circuit includes a polygonal approximation data generating means, a correcting data table having data corresponding to the difference between the polygonal approximation data and desired data and adder means for adding the polygonal approximation data and the output data of said correcting data table, and said control data controls the output data of said correcting data table.

6. A digital signal processing circuit according to claim 4, wherein said gamma correction circuit includes a step approximation data generating means, a correcting data table having data corresponding to the difference between the step approximation data and desired data and adder means for adding the step approximation data and the output data of said correcting data table, and said control data controls the output data of said correcting data table.

7. A digital signal processing circuit according to claim 2, wherein said operating circuit of one of said signal processing blocks includes an aperture correction for producing an aperture correction signal from the digital video signal, adder means for adding the aperture correction signal to said digital video signal, a level compression circuit supplied with the output of said aperture correction circuit, and said control data controls the level of said aperture correction signal and the characteristics of said level compression circuit.

8. A digital signal processing circuit according to claim 2, wherein said operating circuit of one of said signal processing circuit blocks includes a white clip circuit and a dark clip circuit, and said control data controls the white clip level and the dark clip level.