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Push-pull readout of dual gate CID arrays

  • US 4,862,276 A
  • Filed: 10/07/1988
  • Issued: 08/29/1989
  • Est. Priority Date: 10/07/1988
  • Status: Expired due to Fees
First Claim
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1. In an IR sensitive charge injection device (CID), the combination comprising:

  • (A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, said configuration producing capacitive coupling (CRC) between the row gate and column gate at each pixel site, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line,(B) a readout circuit comprising;

    (a) a source (VRT) of row transfer potentials and m controllable row transfer switches (TS1-m) for injecting signal charge into the substrate and transferring charge via the column line during readout,(b) shift register means (SRO,SRE) coupled to said row transfer switches for connecting a respective (jth) row line to said source (VRT) to begin injection, injection (duration ti) terminating with disconnection of said (jth) row line from said source (VRT)(c) row reset means including a source (VRB) of row bias potentials and m controllable row bias reset switches (RS1-m), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange between column and row gates at a site, said reset switches being timed to disconnect said (jth) row from said source VRB when injection of said jth row begins, the reconnection of said (jth) row line to said source (VRB) for reset occurring at the same instant that the (j+1)th row line is connected to said source (VRT) to begin injection of said (j+1)th row line,(d) n column video processors, each kth processor comprising;

    (1) a gain amplifier (A1k) having the input thereof coupled to the (kth) column line at a first node (N1k),(2) column reset means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0k), for applying a column bias potential (VCB) to said first node (N1k) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site,(3) means including a series connected capacitor (C1k) and a shunt connected switch (S1k) coupled to the output of said gain amplifier for taking a first sample, means including a series connected switch (S3l) and a shunt connected a capacitor (C3k) coupled to the output of said first sample taking means for taking a second sample correlated to the first sample, and(e) timing means including a timing generator for timing the operation of said shift register and said reset switches, the readout of each selected site (jth row, kth column) being effected by switches TSj, RSj, S0k, S1k and S3k,the switches S0k and S1k being closed to reset the first node (N1k) to start readout of the jth row, switch S0k being opened after resetting, switch S1k being opened after settling to finish charging capacitor C1k to obtain a first sample, followed by closure of the jth row transfer switch (TSj) to inject signal charge into said substrate and to transfer charge to and from the column gates, said switch S3k being closed prior to the opening of the jth row transfer switch to obtain a second sample correlated with the first sample, closure of switch S0k at the end of injection resetting the first node (N1k) to terminate readout of the jth pixel,the resetting of the jth row, which produces a negative going pulse due to said capacitive coupling (CRC), simultaneous with injection of said (j+1)th row, which produces a positive going pulse due to said capacitive coupling (CRC), cancelling the extraneous injection pedestal and reducing the voltage excursion at the input of said amplifier (A1k).

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