Push-pull readout of dual gate CID arrays
First Claim
1. In an IR sensitive charge injection device (CID), the combination comprising:
- (A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, said configuration producing capacitive coupling (CRC) between the row gate and column gate at each pixel site, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line,(B) a readout circuit comprising;
(a) a source (VRT) of row transfer potentials and m controllable row transfer switches (TS1-m) for injecting signal charge into the substrate and transferring charge via the column line during readout,(b) shift register means (SRO,SRE) coupled to said row transfer switches for connecting a respective (jth) row line to said source (VRT) to begin injection, injection (duration ti) terminating with disconnection of said (jth) row line from said source (VRT)(c) row reset means including a source (VRB) of row bias potentials and m controllable row bias reset switches (RS1-m), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange between column and row gates at a site, said reset switches being timed to disconnect said (jth) row from said source VRB when injection of said jth row begins, the reconnection of said (jth) row line to said source (VRB) for reset occurring at the same instant that the (j+1)th row line is connected to said source (VRT) to begin injection of said (j+1)th row line,(d) n column video processors, each kth processor comprising;
(1) a gain amplifier (A1k) having the input thereof coupled to the (kth) column line at a first node (N1k),(2) column reset means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0k), for applying a column bias potential (VCB) to said first node (N1k) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site,(3) means including a series connected capacitor (C1k) and a shunt connected switch (S1k) coupled to the output of said gain amplifier for taking a first sample, means including a series connected switch (S3l) and a shunt connected a capacitor (C3k) coupled to the output of said first sample taking means for taking a second sample correlated to the first sample, and(e) timing means including a timing generator for timing the operation of said shift register and said reset switches, the readout of each selected site (jth row, kth column) being effected by switches TSj, RSj, S0k, S1k and S3k,the switches S0k and S1k being closed to reset the first node (N1k) to start readout of the jth row, switch S0k being opened after resetting, switch S1k being opened after settling to finish charging capacitor C1k to obtain a first sample, followed by closure of the jth row transfer switch (TSj) to inject signal charge into said substrate and to transfer charge to and from the column gates, said switch S3k being closed prior to the opening of the jth row transfer switch to obtain a second sample correlated with the first sample, closure of switch S0k at the end of injection resetting the first node (N1k) to terminate readout of the jth pixel,the resetting of the jth row, which produces a negative going pulse due to said capacitive coupling (CRC), simultaneous with injection of said (j+1)th row, which produces a positive going pulse due to said capacitive coupling (CRC), cancelling the extraneous injection pedestal and reducing the voltage excursion at the input of said amplifier (A1k).
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Abstract
The invention relates to charge injection devices (CID) for sensing IR image intensity information obtained from a two dimensional array of dual-gate sensing sites on an InSb or HgCdTe substrate, and more particularly to a novel push-pull readout circuit which eliminates the pedestal due to capacitive coupling between gates on the same pixel of a dual gate CID. The CID is scanned in rows and read out in parallel columns. Pedestal cancellation is achieved in one example by resetting the prior row as a selected row is injected. In a second example pedestal cancellation is achieved by adding an additional row which is reset as each row is injected, while in a third example a pedestal cancellation network is provided associated with each column output circuit.
27 Citations
5 Claims
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1. In an IR sensitive charge injection device (CID), the combination comprising:
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(A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, said configuration producing capacitive coupling (CRC) between the row gate and column gate at each pixel site, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line, (B) a readout circuit comprising; (a) a source (VRT) of row transfer potentials and m controllable row transfer switches (TS1-m) for injecting signal charge into the substrate and transferring charge via the column line during readout, (b) shift register means (SRO,SRE) coupled to said row transfer switches for connecting a respective (jth) row line to said source (VRT) to begin injection, injection (duration ti) terminating with disconnection of said (jth) row line from said source (VRT) (c) row reset means including a source (VRB) of row bias potentials and m controllable row bias reset switches (RS1-m), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange between column and row gates at a site, said reset switches being timed to disconnect said (jth) row from said source VRB when injection of said jth row begins, the reconnection of said (jth) row line to said source (VRB) for reset occurring at the same instant that the (j+1)th row line is connected to said source (VRT) to begin injection of said (j+1)th row line, (d) n column video processors, each kth processor comprising; (1) a gain amplifier (A1k) having the input thereof coupled to the (kth) column line at a first node (N1k), (2) column reset means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0k), for applying a column bias potential (VCB) to said first node (N1k) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site, (3) means including a series connected capacitor (C1k) and a shunt connected switch (S1k) coupled to the output of said gain amplifier for taking a first sample, means including a series connected switch (S3l) and a shunt connected a capacitor (C3k) coupled to the output of said first sample taking means for taking a second sample correlated to the first sample, and (e) timing means including a timing generator for timing the operation of said shift register and said reset switches, the readout of each selected site (jth row, kth column) being effected by switches TSj, RSj, S0k, S1k and S3k, the switches S0k and S1k being closed to reset the first node (N1k) to start readout of the jth row, switch S0k being opened after resetting, switch S1k being opened after settling to finish charging capacitor C1k to obtain a first sample, followed by closure of the jth row transfer switch (TSj) to inject signal charge into said substrate and to transfer charge to and from the column gates, said switch S3k being closed prior to the opening of the jth row transfer switch to obtain a second sample correlated with the first sample, closure of switch S0k at the end of injection resetting the first node (N1k) to terminate readout of the jth pixel, the resetting of the jth row, which produces a negative going pulse due to said capacitive coupling (CRC), simultaneous with injection of said (j+1)th row, which produces a positive going pulse due to said capacitive coupling (CRC), cancelling the extraneous injection pedestal and reducing the voltage excursion at the input of said amplifier (A1k). - View Dependent Claims (2)
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3. In an IR sensitive charge injection device (CID), the combination comprising:
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(A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m+1 rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, said configuration producing capacitive coupling (CRC) between the row gate and column gate at each pixel site, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line, (B) a readout circuit comprising; (a) a source (VRT) of row transfer potentials and (m+1) controllable row transfer switches the (TS1-m, TSd), for injecting signal charge into substrate and transferring charge via the column line during readout, of row bias potentials and (m+1) controllable row bias reset switches (RS1-m RSd), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange, between column and row gates at a site, (c) row selection means including a shift register (SR'"'"') having m outputs for controlling said row transfer switches (TS1-m) for selected (jth) member of said set of m row lines to said source (VRT) to begin injection, injection (duration ti) terminating with disconnection of said (jth) row line from said source (VRT), and for controlling said row reset switches (RS1-m) for disconnecting said (jth) row from said row bias source (VRB) when injection of said selected jth row begins and for connecting said (jth) row to said bias source (VRB) when injection of said selected jth row ends, said row bias reset switch RSd connecting said (m+1)th row line to said source (VRB) simultaneously with the connection of each selected (jth) row to said source (VRT), and said row transfer switch TSd connecting said (m+1)th row line to said source (VRT) simultaneously with the connection of each selected (jth) row to said source (VRB), (d) n column video processors, each kth processor comprising; (1) a gain amplifier (A1k) having the input thereof coupled to the (kth) column line at a first node (N1k), (2) column reset means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0k), for applying a column bias potential (VCB) to said first node (N1k) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site, (3) means including a series connected capacitor (C1k) and a shunt connected switch S1k coupled to the output of said gain amplifier, for taking a first sample, (4) means including a series connected switch (S3k)and a shunt connected capacitor C3k) coupled to the output of said first sample taking means for taking a second sample correlated with the first sample, and (e) timing means including a timing generator for timing the operation of said shift register and said reset switches, the readout of each selected site (jth row, kth column) being effected by switches TSj and TSd, RSj and RSd, S0k, S1k, and S3k, the switches S0k and S1k being closed to reset the first node (N1k) to start readout of the jth being opened after settling to finish charging capacitor C1k to obtain a just sample, followed by closure of the jth row transfer switch (TSj) to inject signal charge into said substrate and to transfer charge to and from the column gates, said switch S3k being closed prior to the opening of the jth row transfer switch to obtain a second sample correlated with the first sample, closure of switch S0k at the end of injection resetting the first node (N1k) to terminate readout of the jth pixel, the resetting of the (m+1)th row, simultaneous with injection of each row, and the injection of the (m+1)th row, simultaneous with reset of each row, cancelling the injection pedestal and reducing the voltage excursion on all N1 modes. - View Dependent Claims (4)
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5. In an IR sensitive charge injection device (CID), the combination comprising:
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(A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, said configuration producing capacitive coupling (CRC) between the row gate and column gate at each pixel site, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line, (B) a readout circuit comprising; (a) a source (VRT) of controllable row transfer switches (TS1-m), for injecting signal charge into the substrate and transferring charge via the column line during readout, (b) row reset means including a source (VRB) of row bias potentials and m controllable row bias reset switches (RS1-m), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange between column and row gates at a site, (c) row selection means including a shift register (SR'"'"') having m outputs for controlling said row transfer switches (TS1-m) successively connecting a selected (jth) row line to said source (VRT) to begin injection, injection (duration ti) terminating with disconnection of said (jth) row line from said source (VRT); and
for controlling said row reset switches (RS1-m) for disconnecting said (jth) row from said row bias source (VRB) when injection of said selected jth row begins and for connecting said (jth) row to said bias source (VRB) when injection of said selected jth row ends,(d) n column video processors, each kth processor comprising; (1) a gain amplifier (A1k) having the input thereof coupled to the (kth) column line at a first node (N1k), (2) column reset means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0k), for applying a column bias potential (VCB) to said first node (N1k) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site, (3) means including a series connected capacitor (C1k) and a shunt connected switch S1k coupled to the output of said gain amplifier, for taking a first sample, (4) means including a series connected switch (S3k) and a shunt connected capacitor (C3k) coupled to the output of said first sample taking means for taking a second sample correlated with the first sample, and (5) a pedestal cancellation network comprising (i) a source of pedestal cancellation voltage (VC) (ii) a capacitor (C0k) having one terminal coupled to a node N0k and the other to the node N1k (iii) a first pedestal cancellation switch SC1k connected between said source VC and said node N0k (iv) an inverter UCk having the output connected to control said first switch SC1k (v) a second pedestal cancellation switch SC2k connected between ground and said node N0k (e) timing means including a timing generator for timing the operation of said shift register, said reset switches and said pedestal cancellation network, the readout of each selected site (jth row, kth column) being effected by switches TSj, RSj, S0k, S1k and S3k, and pedestal cancellation being effected by switches SC1k and SC2k the switches S0k and S1k being closed to reset the first node (N1k) to start readout of the jth row, switch S0k being opened after resetting, switch S1k being opened after settling to finish charging capacitor C1k to obtain a first sample, followed by closure of the jth row transfer switch (TSj) to inject signal charge into said substrate and to transfer charge to and from the column gates, said switch S3k being closed prior to the opening of the jth row transfer switch to obtain a second sample correlated with the first sample, closure of switch S0k at the end of injection resetting the first node to terminate readout of the jth pixel, switch SC1k being opened and switch SC2k being closed simultaneously with injection of each row, and switch SC1k being closed and switch SC2k being opened simultaneously with the resetting of each row to cancel the injection pedestal and reduce the voltage excursion on all N1 nodes.
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Specification