Architecture for a distributive microprocessing system

• US 4,862,350 A
• Filed: 04/24/1987
• Issued: 08/29/1989
• Est. Priority Date: 08/03/1984
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Williams, Crawford E., Orr, Michael A.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Anderson, Lawrence E.
• Application Number:
  US07/042,556
• Time in Patent Office: 858 Days
• Field of Search: 364/134, 364/200 MS File, 364/900 MS File
• US Class Current: 709/213
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

An architecture for interconnecting a plurality of remote processors to a primary processor. The architecture provides an improved interface and a communication channel for interconnecting the processors. The interface includes a commonly shared buffer which stores messages to be exchanged between the primary processor and the remote processors. A controller (microprocessor based) is provided to manage the buffer and the communication channel. The controller gives the primary processor direct access to the buffer periodically. Likewise, the controller uses a polling technique to enable each remote processor to communicate, over the communication channel, with the shared buffer.

Claims

1. In a multiprocessing system having a plurality of secondary device control processors for processing data generated from particular devices and to provide the data to a satellite terminal and a remote primary processor for further processing an improved interface for controlling and transmitting data between the primary processor and the secondary processors, said improved interface comprising:

a common buffer for storing data and for enabling messages to be exchanged between the primary processor and the secondary device control processors, the satellite terminal;

a serial I/O link for transmitting data;

a first set of tri-state buffers connected to the common buffer;

a first microprocessor interconnecting the first set of tri-state buffers and the serial I/O link;

said first microprocessor dedicated to managing said common buffer and formatting messages placed in said common buffer for transmission on said serial I/O link and placing messages received on said link into the common buffer;

a primary microprocessor;

a second set of tri-state buffers interconnecting the common buffer and the primary microprocessor such that said primary processor can be isolated from said common buffer;

a first decode logic means connected to the first microprocessor;

said first decode logic means responsive to signals outputted from the first microprocessor for generating a first control signal;

a first latch means connected to the first decode means and responsive to the first control signal to generate a first interrupt signal for setting said second set of tri-state buffers in a first state which allows the primary microprocessor to access the common buffer and interrupts the primary microprocessor;

a second decode means connected to the primary microprocessor and responsive to signals outputted from the primary microprocessor to generate a second control signal;

a second latch means connected to the second decode means and responsive to the second control signal to generate a second interrupt signal for interrupting the first microprocessor;

an inverter circuit means connected to the first latch means and responsive to the first interrupt signal to generate a third control signal for setting the first set of tri-state buffers in a second state opposite to the state of the second set of tristate buffers with said second state inhibiting the first microprocessor from accessing the common buffer;

a thrid latch means connected to the second and first decode means;

said third latch means responsive to be set to a first state by electrical signals outputted from said second decode means when the primary microprocessor terminates its use of the common buffer and responsive to be reset to a second state by electrical signals outputted from said first decode means when the first microprocessor resumes control of said common buffer;

whereby messages from said primary processor to said satellite terminal and said secondary device control processors are placed in said common buffer by the primary processor while said first microprocessor is isolated from said common buffer, and said first microprocessor places received messages from said satellite terminal and said secondary device control processors into said common buffer while said primary processor is isolated from said common buffer.