Digital signal processing apparatus
First Claim
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1. A digital signal processing apparatus comprising:
- a host processor having a data bus and an address bus;
first and second dual port memory elements, wherein each of said memory elements has first and second data and address interfaces, said first data interfaces of said first and second memory elements being coupled to said host processor data bus, and said first address interfaces of said first and second memory elements being coupled to said host processor address bus; and
first and second coprocessors each being for performing predetermined arithmetic functions required by digital signal processing applications, and each having a data bus and a data address bus, said first coprocessor data bus being coupled to said first memory element second data interface, said first coprocessor data address bus being coupled to said first memory element second address interface, said second coprocessor data bus being coupled to said second memory element second data interface, and said second coprocessor data address bus being coupled to said second memory element second address interface.
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Abstract
A digital signal processing apparatus having a host processor interfaced to a plurality of signal processing coprocessors through dual port memory elements is disclosed. Coprocessors represent microcoded machines wherein low level instructions directed toward the mechanics of performing a specific signal processing algorithm are contained in microcode. Thus, the host processor programs coprocessors using higher level functional instructions. Each of the coprocessors has a multiply-accumulator, a barrel shifter, an address generator, a hardware loop counter, and a microsequencer.
130 Citations
15 Claims
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1. A digital signal processing apparatus comprising:
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a host processor having a data bus and an address bus; first and second dual port memory elements, wherein each of said memory elements has first and second data and address interfaces, said first data interfaces of said first and second memory elements being coupled to said host processor data bus, and said first address interfaces of said first and second memory elements being coupled to said host processor address bus; and first and second coprocessors each being for performing predetermined arithmetic functions required by digital signal processing applications, and each having a data bus and a data address bus, said first coprocessor data bus being coupled to said first memory element second data interface, said first coprocessor data address bus being coupled to said first memory element second address interface, said second coprocessor data bus being coupled to said second memory element second data interface, and said second coprocessor data address bus being coupled to said second memory element second address interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of processing first and second portions of digital representations of analog signals, said method comprising the steps of:
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making the first and second portions available to a host processor; transferring the first portion from the host processor through a first port of a first dual port memory to the first dual port memory; transferring the second portion from the host processor through a first port of a second dual port memory to the second dual port memory; operating on the first portion using a first coprocessor which couples to a second port of the first dual port memory; and operating on the second portion using a second coprocessor which couples to a second port of the second dual port memory. - View Dependent Claims (13, 14)
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15. A digital signal processing apparatus comprising:
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a host processor having a data bus and an address bus; first and second dual port memory elements, wherein each of said memory elements has first and second data and address interfaces, said first data interfaces of said first and second memory elements being coupled to said host processor data bus, and said first address interfaces of said first and second memory elements being coupled to said host processor address bus; first and second coprocessors wherein; each of said coprocessors has a data bus and a data address bus, said first coprocessor data bus being coupled to said first memory element second data interface, said first coprocessor data address bus being coupled to said first memory element second address interface, said second coprocessor data bus being coupled to said second memory element second data interface, and said second coprocessor data address bus being coupled to said second memory element second address interface; and said first coprocessor comprises; a first data register having an input coupled to said first coprocessor data bus and an output; a second data register having an input coupled to said first coprocessor data bus and an output; a multiplier-accumulator having a first input coupled to said first data register output and a second input coupled to said second data register output; a microsequencer having an output coupled to said first and second data registers and having a jump control input ; an address generator having an input coupled to said microsequencer output and an output coupled to said first coprocessor data address bus; a loop counter having an input coupled to said microsequencer output and an output coupled to microsequencer jump control input; and a barrel shifter having a data input coupled to said first coprocessor data bus, a control input coupled to said microsequencer control output, and a shift output coupled to said first coprocessor data bus.
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Specification