Quotient phase-shift processor for digital phase-locked-loops

• US 4,862,485 A
• Filed: 10/14/1987
• Issued: 08/29/1989
• Est. Priority Date: 10/14/1987
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Guinea, Jesus, Wong, Hee
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/108,371
• Time in Patent Office: 685 Days
• Field of Search: 375/81, 375/108, 375/110, 375/119, 375/120, 360/51, 328/72, 328/74, 328/155, 331/1 A, 331/18
• US Class Current: 375/376
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814

Abstract

A quotient phase-shift processor is provided which includes novel techniques for realizing phase corrections of a digital phase-locked-loop. A binary phase-detector of the "early-late" type is combined with range-phase-detector circuitry to generate a variable lock acquisition speed. Phase measure and speed control are performed by incremental manipulation which feeds a novel "quotient" processor. The quotient processor integrates the incremental phase errors and performs phase corrections in a nonperiodic fashion, resulting in lower effective proportional loop gain than that provided in standard phase-locked-loops. Wide capture-range and low jitter are obtained by dynamically varying a loop time constant. Pattern dependent noise is reduced by a novel gating technique. High crystal-frequency requirements are reduced, extending the spectral application of digital phase-locked-loops.

Claims

1. A quotient digital phase locked loop, comprising:

(a) binary phase detector means which compares an incoming signal to an internally-generated baud clock signal to provide a phase error bit sequence which indicates whether the phase of the incoming signal is early or late with respect to the phase of the baud clock signal; and

(b) a digital controlled clock which integrates the phase error bit sequence to effect nonperiodic phase manipulation of the baud clock signal.

2. A quotient digital phase locked loop as in claim 1 wherein the digital controlled clock includes quotient processor means which divides a sequential accumulator value by a divisor constant each period defined by a crystal clock input to the digital controlled clock, the division resulting in a quotient value and a remainder value, the quotient value being only 0 or 1, the remainder value for successive divisions being added until the sum of the remainder values equals or exceeds a predetermined value, the quotient value equalling 0 only when the remainder value sum equals or exceeds the predetermined value, resulting in a quotient value bit stream comprising a sequence of 1s and nonperiodic 0s, the quotient value bit stream being utilized to effect nonperiodic phase manipulation of the baud clock signal.

3. A quotient digital phase locked loop as in claim 1 and further including a range-phase detector which generates an output indicative of whether the phase of the output of the digital controlled clock is within a predetermined phase range.

4. A quotient digital phase locked loop as in claim 3 wherein the range-phase-detector output is utilized to dynamically change the frequency of phase manipulation of the baud clock signal.

5. A quotient digital phase locked loop as in claim 1 and further including means for avoiding phase manipulation during a predefined condition.

6. A quotient digital phase locked loop as in claim 1 and further including means for disabling phase manipulation during a predetermined period.

7. A quotient digital phase locked loop as in claim 1 and further including means for dynamically varying the loop time constant to obtain wide capture range and low jitter.

8. A quotient digital phase locked loop as in claim 5 wherein the predefined condition is a lack-of-strobe condition.

9. A quotient digital phase locked loop as in claim 6 wherein the predetermined period is a period when no timing information is available.