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Electronic payment process using a smart card

  • US 4,864,110 A
  • Filed: 06/01/1988
  • Issued: 09/05/1989
  • Est. Priority Date: 10/16/1986
  • Status: Expired due to Term
First Claim
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1. Electronic payment process using an Eprom card incorporating binary storage cells with a logic content equal either to 0 or to 1, whereby each cell can be electrically laced by irreversibly passing its content from one state to another, said process being characterized in that:

  • the storage cells are grouped into elements grouping at least two cells, each element being locatable by an address and having a parity, one element being said to be even when the number of its cells in state 1 is even and is said to be odd when the number of its cells in state 1 is odd,the balance of the card is the number of non-zero elements having a first parity and an address below the address of the element of opposite parity with the lowest address and which is called a "terminal" or, if the latter element does not exist, the number of non-zero elements of said first parity in the memory,to debit the card and reduce said balance, the terminal is moved towards a lower address whilst creating a new opposite parity element with a lower address than the terminal to be displaced, whereby said new element becomes the new terminal, the number P of debited units being equal to the number of first parity elements located between the old terminal and the new terminal, plus 1,to credit the card and increase the balance, the terminal is moved towards a higher address, whilst again giving to possible elements which already have said opposite parity and having an address higher than the terminal to be displaced said first parity and this takes place by lacing a new cell and by creating a new element having the second parity with a higher address than the terminal to be displaced, unless said element already has said parity, in which case it is left as it is, the number K of units credited to the card being equal to the number of elements having the first parity located between the old terminal and the new terminal, plus 1.

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