Electronic payment process using a smart card

• US 4,864,110 A
• Filed: 06/01/1988
• Issued: 09/05/1989
• Est. Priority Date: 10/16/1986
• Status: Expired due to Term

• Current Assignee: Etat Francais/Telediffusion De France
• Original Assignee: Etat Francis/Telediffusion De France
• Inventors: Guillou, Claude L.
• Primary Examiner(s): Pitts, Harold I.
• Application Number:
  US07/214,729
• Time in Patent Office: 461 Days
• Field of Search: 235/379, 235/380
• US Class Current: 235/380
• CPC Class Codes: G06Q 20/3433 the counter having monetary units
• CPC Class Codes: G07F 7/02 by keys or other credit registering devices
• CPC Class Codes: G07F 7/0866 by active credit-cards adapted therefor G07F7/1008 takes precedence

Abstract

The storage cells are grouped into elements grouping at least two cells, each element being locatable by an address and having a parity. The balance of the card is the number of non-zero even elements with an address below the address of the odd element with the lowest address and which is called the "terminal". In order to debit the card and reduce said balance, the terminal is moved towards a lower address, while creating a new old element of lower address than the terminal to be displaced. In order to credit the card and increase this balance, the terminal is moved towards a higher address, while again giving to possible odd elements with a higher address than the terminal to be displaced an even character and while creating a new odd element with a higher address than the terminal to be displaced.

Claims

1. Electronic payment process using an Eprom card incorporating binary storage cells with a logic content equal either to 0 or to 1, whereby each cell can be electrically laced by irreversibly passing its content from one state to another, said process being characterized in that:

the storage cells are grouped into elements grouping at least two cells, each element being locatable by an address and having a parity, one element being said to be even when the number of its cells in state 1 is even and is said to be odd when the number of its cells in state 1 is odd,

the balance of the card is the number of non-zero elements having a first parity and an address below the address of the element of opposite parity with the lowest address and which is called a "terminal" or, if the latter element does not exist, the number of non-zero elements of said first parity in the memory,

to debit the card and reduce said balance, the terminal is moved towards a lower address whilst creating a new opposite parity element with a lower address than the terminal to be displaced, whereby said new element becomes the new terminal, the number P of debited units being equal to the number of first parity elements located between the old terminal and the new terminal, plus 1,

to credit the card and increase the balance, the terminal is moved towards a higher address, whilst again giving to possible elements which already have said opposite parity and having an address higher than the terminal to be displaced said first parity and this takes place by lacing a new cell and by creating a new element having the second parity with a higher address than the terminal to be displaced, unless said element already has said parity, in which case it is left as it is, the number K of units credited to the card being equal to the number of elements having the first parity located between the old terminal and the new terminal, plus 1.

2. Process according to claim 1, characterized in that the first parity is the even parity and the opposite parity is the odd parity, the terminal being constituted by the odd element with the lowest address.

3. Process according to claim 1, characterized in that the storage elements can either be pairs, or nibbles, or bytes, or more complex words, or a combination of these various elements.

4. Process according to claim 1, characterized in that the card is of the microprocessor type with a memory having a reserved zone constituted by bytes, the basic byte of address A and the following byte of address A+1 not being available for payment, the zone reserved to the payments and to reloading operations ranging from the byte of address A+2 to the last byte of address Amax.

5. Process according to claim 3, characterized in that the reserved zone comprises M words constituted in each case by N bytes, each word starting with a first byte, whose most significant nibble is determined and the same for all the words, the elements usable for the payment thus being constituted by the least significant nibble belonging to the first byte of each word and the following bytes of each word.