SCSI converter

• US 4,864,291 A
• Filed: 06/21/1988
• Issued: 09/05/1989
• Est. Priority Date: 06/21/1988
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Korpi, James E.
• Primary Examiner(s): Yusko, Donald J.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/209,672
• Time in Patent Office: 441 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 307/260, 307/261, 307/262, 307/276, 307/151, 370/124, 370/85, 370/17, 370/93, 340/825.5, 340/825.05, 340/825.51
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4226 with asynchronous protocol
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration

Abstract

A converter for coupling a single-ended and a differential SCSI bus that facilitates the use of the ARB, SELECTION, and RESELECTION phases of the SCSI protocol.

Claims

1. A converter for selectively transferring signals between a single ended line of an internal bus and a differential line pair of an external bus, with both buses utilizing the SCSI bus protocol that included BUSFREE (BF), ARBITRATION (ARB), and SELECTION phases and with both buses including BUSY (BSY), SLECT (SEL) and DATA lines for transmitting BSY, SEL, and device ID signals, respectively, where devices on both sides, internal and external, of the converter may assert BSY and their device ID signals during the ARB phase, a subsystem for facilitating the transfer of a BSY signal during the ARB phase from either side to the other and for releasing the BSY line on both sides during the SELECTION phase, said subsystem comprising:

a first driver, having an input port adapted to receive a first input signal, for asserting a differential BSY signal on the external differential BSY line pair when said first input signal is asserted;

a first receiver, comprising a gate, having first and second inputs coupled to the internal BSY line of said internal bus and a first signal line that transmits a first signal, respectively, and an output coupled to the input port of said first driver, for transferring a BSY signal from the internal BSY line to the input port of said first driver only when said first signal is set;

a second receiver, having input ports coupled to the differential BSY line pair and an output port coupled to an EXT.BSY signal line that transmits an EXT.BSY signal, for asserting said EXT.BSY signal when a BSY signal is asserted on said differential external BSY line pair;

a second driver, comprising a second gate, having first and second inputs coupled to said EXT.BSY signal line and a second signal line that transmits a second signal, respectively, and an output coupled to the internal BSY line of said internal bus, for transferring an EXT.BSY signal on said EXT.BSY signal line to the internal BSY line only if said second signal is set;

means for setting said first signal when no signals are asserted on the internal BSY and internal SEL lines, thereby indicating that the buses are in said BUSFREE phase;

means for setting said second signal only if a device coupled to the external bus asserts its device ID and said first signal is set; and

means for resetting said first signal and said second signal when a device on either the internal or external side asserts the SEL signal to initiate the SELECTION phase.

2. A converter for selectively transferring signals between a single ended line of an internal bus and a differential line pair of an external bus, with both buses utilizing the SCSI bus protocol that includes BUSFREE (BF), ARBITRATION (ARB), and SELECTION phases and with both buses including BUSY (BSY), SELECT (SEL) and DATA lines for transmitting BSY, SEL, and device ID signals, respectively, and where devices on both sides, internal and external, of the converter may assert BSY and their device ID signals during the ARB phase, a subsystem for facilitating the transfer of a BSY signal during the ARB phase from either side to the other and for releasing the BSY line on both sides during the SELECTION phase, said subsystem comprising:

means, adapted to receive a first PASS signal, for transferring a BSY signal assert on the internal BSY line to the external differential BSY line pair only when said first PASS signal is set;

means, adapted to receive a second PASS signal, for transferring a BSY signal asserted on the external differential BSY line pair to the internal BSY line only when said second PASS signal is set;

means for setting said first PASS signal only when no signals are asserted on the internal BSY and SEL lines to indicate that the buses are in the BF phase;

means for setting said second PASS signal only when said first PASS signal is set and a device on the external side is asserting BSY; and

means for resetting said first and second PASS signals in response to a device on either the internal or external side asserting the SEL signal to initiate the SELECTION phase.

3. A converter for selectively transferring signals between a single ended line of an internal bus and a differential line pair of an external bus, with both buses utilizing the SCSI bus protocol that includes BUSFREE (BF), ARBITRATION (ARB), and SELECTION or RESELECTION phases and with both buses including BUSY (BSY), SELECT (SEL) and DATA lines for transmitting BSY, SEL, and device ID signals, respectively, where initiator and target devices may be coupled to the internal bus and target devices may be coupled to the external bus and where devices on both sides, internal and external, of the converter may assert BSY and their device ID signals during the ARB phase, a subsystem for facilitating the transfer of a BSY signal during the RESELECTION phase, said subsystem comprising:

means, adapted to receive a first PASS signal, for transferring a BSY signal asserted on the internal BSY line to the external differential BSY line pair only when said first PASS signal is set;

means, adapted to receive a second PASS signal, for transferring a BSY signal asserted on the external differential BSY line pair to the internal BSY line only when said second PASS signal is set;

means for storing an indication of whether a target device asserting the SEL signal during the ARB phase was located on the internal side or the external side;

means for setting said first PASS signal, during the RES phase, when an initiator device asserts the BSY signal; and

means, responsive to said indication, for resetting said first PASS signal, set during the RES phase, and setting said second PASS signal when a target device asserts BSY only if a target device on said external side asserted SEL during the ARB phase.

4. A converter for selectively transferring signals between a single ended line of an internal bus and a differential line pair of an external bus, with both buses utilizing the SCSI bus protocol that includes BUSFREE (BF), ARBITRATION (ARB), and SELECTION phases and with both buses including BUSY (BSY), SLECT (SEL) and DATA lines for transmitting BSY, SEL, and device ID signals, respectively, where devices on both sides, internal and external, of the converter may assert BSY and their device ID signals during the ARB phase, a subsystem for facilitating the transfer of a BSY signal during the ARB phase from either side to the other and for releasing the BSY line on both sides during the SELECTION phase, said subsystem comprising:

an external receiver circuit that converts a differential external BSY signal into a single ended BSY signal;

an external gate circuit that receives the single ended BSY signal and transfers the single ended BSY signal to the single ended internal BSY line only when an external gate signal is set;

an internal driver circuit, having an enable port coupled to an enable line for receiving a signal asserted on said enable line, that asserts a differential external BSY signal only when said signal is asserted on said enable line;

an internal gate that receives the single ended internal BSY signal and transfers the single ended internal BSY signal to said enable line only when an internal gate signal is set;

an internal logic circuit, with inputs for receiving internal SEL and BSY signal and the external SEL and BSY signals, that sets the internal gate signal during the BF state only when both the internal BSY and SEL signals are not asserted and resets the internal gate signal when either the internal or external SEL signal is asserted during the SELECTION phase;

an external logic circuit, having inputs for receiving said internal gate signals and external device ID signals, that sets the external gate signal only when the internal gate signal is set and an external device ID signal is asserted and resets said external gate signal only when said internal gate or device ID signals are reset or released.

5. A converter for selectively transferring signals between a single ended line of an internal bus and a differential line pair of an external bus, with both buses utilizing the SCSI bus protocol that included BUSFREE (BF), ARBITRATION (ARB), and RESELECTION phases and with both buses including BUSY (BSY), SLECT (SEL) and DATA lines for transmitting BSY, SEL, and device ID signals, respectively, where initiator and target devices may be coupled to the internal bus and target devices may be coupled to the external bus and where devices on both sides, internal and external, of the converter may assert BSY and their device ID signals during the ARB phase, a subsystem for facilitating the transfer of a BSY signal during the ARB phase from either side to the other and for releasing the BSY line on both sides during the RESELECTION phase, said subsystem comprising:

an external receiver circuit that converts a differential external BSY signal into a single ended BSY signal;

an external gate circuit that receives the single ended BSY signal and transfers the single ended BSY signal to the single ended internal BSY line only when an external gate signal is set;

an internal driver circuit, having an enable port coupled to an enable line for receiving a signal asserted on said enable line, that asserts a differential external BSY signal only when said signal is asserted on said enable line;

an internal gate that receives the single ended internal BSY signal and transfers the single ended internal BSY signal to said enable line only when an internal gate signal is set;

a logic circuit which sets said internal gate signal and resets said external gate signal when an initiator asserts the internal BSY signal and resets said internal gate signal and sets said external gate signal a fixed time interval after said initiator asserted the internal BSY signal only if a target device on the external side asserted SEL during the ARB phase.