Dram cell and method

• US 4,864,375 A
• Filed: 04/29/1988
• Issued: 09/05/1989
• Est. Priority Date: 02/05/1986
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Teng, Clarence W., Chen, Cheng-Eng D., Mao, Bor-Yen
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/188,729
• Time in Patent Office: 494 Days
• Field of Search: 357/23.6, 357/41, 357/55, 357/49
• US Class Current: 257/302
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

The following detailed description describes a dynamic random access memory (dRAM) cell. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell pass transistor is formed on the sidewalls of a trench containing the cell capacitor; the word and bit lines cross over this trench. The trench extends through an epitaxial layer into a substrate. The epitaxial layer and substrate are separated by a layer which serves as a diffusion barrier. This stacking of the transistor on top of the capcitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. The diffusion barrier allows for the optimal doping of the epitaxial for operation of the transistor and optimal doping of the substrate for operation of the capacitor.

One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench, and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is transferred to the polysilicon capacitor plate transistor with the polysilicon capacitor plate. This connection between source and polysilicon capacitor plate is provided by a buried lateral contact.

Claims

1. A semiconductor electrical device comprising:

a doped substrate;

a diffusion barrier formed substantially at the surface of said substrate, said diffusion barrier preventing the diffusion of dopant atoms from said substrate;

a single crystal semiconductor layer formed on the surface of said diffusion barrier; and

a trench having an opening at the surface of said crystalline semiconductor layer, said trench extending through said diffusion barrier and into said dope substrate;

a capacitor at least partially formed in said trench; and

a transistor having a channel formed in a surface of said single crystal semiconductor layer and being electrically connected to said capacitor.

2. The device of claim 1 wherein said capacitor comprises:

a conductive layer formed in said trench but insulated from said substrate, said conductive layer serving as a first plate of said capacitor, and said substrate serving as a second plate of said capacitor.

3. A semiconductor electrical device comprising:

a doped silicon substrate;

a layer of silicon dioxide formed substantially at the surface of said substrate, said layer of silicon dioxide preventing the diffusion of dopant atoms from said substrate;

a single crystal semiconductor layer formed on the surface of said layer of said layer of silicon dioxide;

a trench having an opening at the surface of said crystalline semiconductor layer and extending through said layer of silicon dioxide into said doped silicon substrate;

a capacitor at least partially formed in said trench; and

a transistor having a channel formed in a surface of said single crystal semiconductor layer and being electrically connected to said capacitor.

4. The device of claim 3 wherein said capacitor comprises;

a conductive layer formed in said trench but insulated from said substrate, said conductive layer serving as a first plate of said capacitor, and said substrate serving as a second plate of said capacitor.