Instruction address producing unit capable of accessing an instruction segment of an extended size
First Claim
1. An instruction address producing unit for use in producing an instruction address in response to an entry descriptor in cooperation with a memory unit which has a plurality of descriptor addresses successively numbered from a reference descriptor address in a segment descriptor segment specified by said entry descriptor so as to store a plurality of instruction segment descriptors in the respective descriptor addresses of said segment descriptor segment, wherein:
- said entry descriptor has, in addition to a reference field for said reference descriptor address, first and second segment identifying fields for specifying first and second descriptor addresses in said segment descriptor segment, said first and said second descriptor addresses being representative of relative addresses from said reference descriptor addressing in segment descriptor segment, respectively;
said instruction address producing unit comprising;
accessing means responsive to said entry descriptor for accessing said memory unit to read first and second instruction segment descriptors out of said memory unit, respectively;
retaining means coupled to said memory unit for retaining said first and said second instruction segment descriptors which are read out of said segment descriptor segment to produce first and second retained instruction segment descriptors, respectively; and
instruction address deriving means coupled to said retaining means for deriving said instruction address from said first and said second retained instruction segment descriptors.
1 Assignment
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Accused Products
Abstract
In an instruction address producing unit for producing an instruction address in response to an entry descriptor in cooperation with a segment descriptor segment (48), the entry descriptor has first and second segment fields (41 and 42) corresponding to first and second instruction descriptors stored in the segment descriptor segment, respectively. The first and the second instruction descriptors are partially read out of the segment descriptor segment to be kept in an instruction segment register (52) and an instruction counter (57), respectively, and to be produced as first and second retained instruction descriptors. An adder circuit (58) adds the first retained instruction descriptor to the second retained instruction descriptor to produce a result of addition as the instruction address. Each of the first and the second instruction descriptors may be an extended segment descriptor.
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Citations
3 Claims
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1. An instruction address producing unit for use in producing an instruction address in response to an entry descriptor in cooperation with a memory unit which has a plurality of descriptor addresses successively numbered from a reference descriptor address in a segment descriptor segment specified by said entry descriptor so as to store a plurality of instruction segment descriptors in the respective descriptor addresses of said segment descriptor segment, wherein:
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said entry descriptor has, in addition to a reference field for said reference descriptor address, first and second segment identifying fields for specifying first and second descriptor addresses in said segment descriptor segment, said first and said second descriptor addresses being representative of relative addresses from said reference descriptor addressing in segment descriptor segment, respectively; said instruction address producing unit comprising; accessing means responsive to said entry descriptor for accessing said memory unit to read first and second instruction segment descriptors out of said memory unit, respectively; retaining means coupled to said memory unit for retaining said first and said second instruction segment descriptors which are read out of said segment descriptor segment to produce first and second retained instruction segment descriptors, respectively; and instruction address deriving means coupled to said retaining means for deriving said instruction address from said first and said second retained instruction segment descriptors. - View Dependent Claims (2, 3)
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Specification