Injection lock clock detection apparatus
First Claim
1. Apparatus for detecting failure or malfunction of a master clock signal comprising, in combination:
- a free-running local oscillator having an unforced oscillation frequency substantially equal to the oscillation frequency of the master clock signal, said local oscillator including means responsive to the master clock signal for producing a lock clock signal synchronized with a logical transition of the master clock signal; and
,a detector circuit including means responsive to the master clock signal and the lock clock signal, respectively, for producing a logical comparison of clock cycle waveforms derived from logical transitions of the master clock signal.
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Abstract
A clock signal produced by a master oscillator is monitored continuously by a detector circuit having a local oscillator which is stabilized in frequency by injection of the master clock signal. The master clock signal is first divided and the divided clock signal is then retimed by the stabilized lock clock signal. The retimed, divided clock signal is then shifted by one complete clock cycle. If the master oscillator clock signal is valid, the retimed clock signal and its shifted counterpart will always assume opposite logic values. The detector circuit generates a logic output signal which assumes a logic 0 value when the two signals are in opposite states, indicating a valid clock condiiton, and a logic 1 value when the signals have the same logic state, indicating an invalid clock condition.
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Citations
12 Claims
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1. Apparatus for detecting failure or malfunction of a master clock signal comprising, in combination:
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a free-running local oscillator having an unforced oscillation frequency substantially equal to the oscillation frequency of the master clock signal, said local oscillator including means responsive to the master clock signal for producing a lock clock signal synchronized with a logical transition of the master clock signal; and
,a detector circuit including means responsive to the master clock signal and the lock clock signal, respectively, for producing a logical comparison of clock cycle waveforms derived from logical transitions of the master clock signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. Apparatus for detecting failure or malfunction of a master clock signal comprising:
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means coupled to the master clock signal for producing a divided clock signal having a period of oscillation which is greater than the period of oscillation of the master clock signal and which is synchronized with logical transitions of the master clock signal; means coupled to the divided clock signal for phase shifting the divided clock signal; and
,means coupled to the divided clock signal and to the phase shifted divided clock signal for producing a comparison of the divided clock signal with its phase shifted counterpart. - View Dependent Claims (8)
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9. In a data processing system in which digital data is transferred from a data source to a data processor synchronously with a master clock signal, the improvement comprising a free-running local oscillator having a natural oscillating frequency substantially equal to the master clock signal frequency, input injection means coupled between said master clock signal and said local oscillator for producing a lock clock signal in synchronous relation with a logical transition of the master clock signal;
- and, a detector circuit including means responsive to the master clock signal and the lock clock signal, respectively, for producing a logical comparison of clock cycle waveforms derived from the master clock signal.
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10. A method for detecting failure or malfunction of a master clock signal comprising the steps:
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producing a divided clock signal having a period of oscillation which is greater than the period of oscillation of the master clock signal and which is synchronized with transitions of the master clock signal; phase shifting the divided clock signal; and
,comparing the divided clock signal with its phase shifted counterpart. - View Dependent Claims (11)
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12. A method for detecting failure or malfunction of a master clock signal comprising the steps:
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producing a free-running local clock signal having an unforced oscillation frequency substantially equal to the oscillation frequency of the master clock signal; synchronizing the local clock signal with a logical transition of the master clock signal; deriving a divided clock signal from the master clock signal; synchronizing the divided clock signal with a logical transition of the local clock signal; and
,producing a logical comparison of clock cycle waveform events which occur in the divided clock signal.
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Specification