Injection lock clock detection apparatus

• US 4,864,574 A
• Filed: 02/04/1988
• Issued: 09/05/1989
• Est. Priority Date: 02/04/1988
• Status: Expired due to Fees

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: Rockwell International Corporation
• Inventors: Pritt, Harley P.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US07/152,080
• Time in Patent Office: 579 Days
• Field of Search: 371/61, 307/269, 375/118, 375/120
• US Class Current: 714/814
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06

Abstract

A clock signal produced by a master oscillator is monitored continuously by a detector circuit having a local oscillator which is stabilized in frequency by injection of the master clock signal. The master clock signal is first divided and the divided clock signal is then retimed by the stabilized lock clock signal. The retimed, divided clock signal is then shifted by one complete clock cycle. If the master oscillator clock signal is valid, the retimed clock signal and its shifted counterpart will always assume opposite logic values. The detector circuit generates a logic output signal which assumes a logic 0 value when the two signals are in opposite states, indicating a valid clock condiiton, and a logic 1 value when the signals have the same logic state, indicating an invalid clock condition.

Claims

1. Apparatus for detecting failure or malfunction of a master clock signal comprising, in combination:

a free-running local oscillator having an unforced oscillation frequency substantially equal to the oscillation frequency of the master clock signal, said local oscillator including means responsive to the master clock signal for producing a lock clock signal synchronized with a logical transition of the master clock signal; and

,

a detector circuit including means responsive to the master clock signal and the lock clock signal, respectively, for producing a logical comparison of clock cycle waveforms derived from logical transitions of the master clock signal.

2. Apparatus for detecting failure or malfunction of a master clock signal as defined in claim 1, including:

means for producing a divided clock signal in response to transitions of the master clock signal, said divided clock signal having a period of oscillation which is greater than the period of oscillation of the master clock signal and which is synchronized with a logical transition of the master clock signal;

means coupled to the divided clock signal for phase shifting the divided clock signal and thereby producing a phase shifted counterpart signal; and

,

means for comparing the divided clock signal with the phase shifted counterpart signal.

3. Apparatus for detecting failure or malfunction of a master clock signal as defined in claim 2, said comparison means comprising an exclusive NOR gate having a first input connected to the divided clock signal, and having a second input connected to the phase shifted counterpart signal.

4. Apparatus for detecting failure or malfunction of a master clock signal as defined in claim 2, said means for producing a divided clock signal comprising a DQ flip-flop having a clock input terminal, a data input terminal, a data output terminal and a data complement output terminal, said data complement output terminal being connected to the data input terminal, and said clock input terminal being connected to receive the master clock signal.

5. Apparatus for detecting failure or malfunction of a master clock signal as defined in claim 2, said means for phase shifting the divided clock signal comprising:

a first DQ flip-flop having a data input terminal connected to the divided clock signal, a clock input terminal and a data output terminal, said clock input signal being connected to said lock clock signal, and having a data output terminal for conducting the divided clock signal as retimed by the lock clock signal; and

,

a second DQ flip-flop having an input data terminal connected to the retimed, divided clock signal and having a clock input terminal connected to the lock clock signal, whereby said divided clock signal is phase shifted by one-half clock cycle in the first DQ flip-flop and by another half clock cycle in the second DQ flip-flop.

6. Apparatus for detecting failure or malfunction of a master clock signal as defined in claim 1, wherein said free-running local oscillator is a relaxation oscillator having an input node, a feedback capacitor being connected to said input node and a clock signal injection resistor being coupled between said input node and said master clock signal for applying an periodic injection signal to said input node.

7. Apparatus for detecting failure or malfunction of a master clock signal comprising:

means coupled to the master clock signal for producing a divided clock signal having a period of oscillation which is greater than the period of oscillation of the master clock signal and which is synchronized with logical transitions of the master clock signal;

means coupled to the divided clock signal for phase shifting the divided clock signal; and

,

means coupled to the divided clock signal and to the phase shifted divided clock signal for producing a comparison of the divided clock signal with its phase shifted counterpart.

8. Apparatus for detecting failure or malfunction of a master clock signal as defined in claim 7, including:

a free-running oscillator for generating a local clock signal having an oscillation frequency substantially equal to the oscillation frequency of the master clock signal;

injection means coupled between the master clock signal and the local clock generator for synchronizing the local clock signal with the master clock signal;

an inverter coupled to the local clock oscillator for producing an inverted the local clock signal; and

,

the inverted local clock signal being coupled to said divided clock producing means and said phase shifting means for gating the divided clock signal and its phase shifted counterpart in synchronous relation with a logical transition of said inverted local clock signal.

9. In a data processing system in which digital data is transferred from a data source to a data processor synchronously with a master clock signal, the improvement comprising a free-running local oscillator having a natural oscillating frequency substantially equal to the master clock signal frequency, input injection means coupled between said master clock signal and said local oscillator for producing a lock clock signal in synchronous relation with a logical transition of the master clock signal;

and, a detector circuit including means responsive to the master clock signal and the lock clock signal, respectively, for producing a logical comparison of clock cycle waveforms derived from the master clock signal.

10. A method for detecting failure or malfunction of a master clock signal comprising the steps:

producing a divided clock signal having a period of oscillation which is greater than the period of oscillation of the master clock signal and which is synchronized with transitions of the master clock signal;

phase shifting the divided clock signal; and

,

comparing the divided clock signal with its phase shifted counterpart.

11. A method for detecting failure or malfunction of a master clock signal as defined in claim 10 including the steps:

generating a local clock signal having an oscillation frequency substantially equal to the oscillation frequency of the master clock signal;

synchronizing the local clock signal with the master clock signal;

inverting the local clock signal; and

,

gating the divided clock signal and its phase shifted counterpart with the inverted local clock signal.

12. A method for detecting failure or malfunction of a master clock signal comprising the steps:

producing a free-running local clock signal having an unforced oscillation frequency substantially equal to the oscillation frequency of the master clock signal;

synchronizing the local clock signal with a logical transition of the master clock signal;

deriving a divided clock signal from the master clock signal;

synchronizing the divided clock signal with a logical transition of the local clock signal; and

,

producing a logical comparison of clock cycle waveform events which occur in the divided clock signal.