Data modulation and demodulation system for magnetic recording system

• US 4,866,544 A
• Filed: 12/08/1987
• Issued: 09/12/1989
• Est. Priority Date: 12/08/1986
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hashimoto, Shuichi
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/130,799
• Time in Patent Office: 644 Days
• Field of Search: 360/39, 360/40, 360/51, 340/347 D
• US Class Current: 360/40
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof

Abstract

A system for modulating and demodulating write data and read data in a magnetic recording system in accordance with a (1,7) RLL method. The modulating and demodulating system includes a first clock pulse generating circuit receiving a reference signal from a recording medium and generating a first clock pulse having a first frequency equal to a data write frequency in accordance with a phase of the reference signal; a second clock pulse generating circuit receiving the first clock pulse and generating a second clock pulse having a second frequency, the second frequency being two-thirds of the first frequency; and a unit for encoding data to be written in accordance with a (1,7) encoding and decoding other data to be read in accordance with a (1,7) decoding, in response to the first and second clock pulses.

Claims

1. A system for modulating and demodulating data written into and read from a magnetic recording medium in accordance with a (1,7) run length limited method, the magnetic medium providing a reference signal, said system comprising:

a first clock pulse generating circuit, operatively connected to receive the reference signal from the recording medium, for generating a first clock pulse having a first frequency equal to a data write frequency in accordance with a phase of the reference signal;

a second clock pulse generating circuit, operatively connected to receive the first clock pulse, for generating a second clock pulse having a second frequency, the second clock pulse being obtained by masking one pulse of every three successive occurrences of the first clock pulse, the second frequency accordingly being two-thirds of the first frequency; and

an encoding and decoding unit, operatively connected to said first and second clock pulse generating circuits, for encoding write data to be written in accordance with (1,7) encoding and for decoding read data read in accordance with (1,7) decoding, in response to the first and second clock pulses.

2. A system according to claim 1, wherein said first clock pulse generating circuit comprises a phase-locked loop circuit, operatively connected to receive the reference signal and to said encoding and decoding unit and said second clock pulse generating circuit.

3. A system according to claim 1, wherein said second clock pulse generating circuit comprises:

a one-third frequency divider, operatively connected to said first clock pulse generating circuit to receive the first clock pulse, for producing a gate pulse having a frequency one-third that of the first frequency of the first clock pulse; and

an OR gate, operatively connected to said first clock pulse generating circuit to receive the first clock pulse and to said one-third frequency divider to receive the gate pulse, for outputting the second clock pulse.

4. A system according to claim 3, wherein said one-third frequency divider comprises first and second flip-flops, having clock terminals operatively connected to said first clock pulse generating circuit to receive the first clock pulse, a first J terminal of said first flip-flop operatively connected to a positive output terminal of said second flip-flop, and a second J terminal of said second flip-flop operatively connected to a negative output terminal of said first flip-flop, the positive output terminal of said second flip-flop being operatively connected to said encoding and decoding unit and said OR gate to supply the first clock pulse.

5. A system according to claim 1, wherein said second clock pulse generating circuit comprises:

a one-third frequency divider, operatively connected to said first clock pulse generating circuit to receive the first clock pulse, for producing a gate pulse having a frequency one-third that of the first frequency of the first clock pulse;

an AND gate, operatively connected to said first clock pulse generating circuit to receive the first clock pulse and to said one-third frequency divider to receive the gate pulse, for producing an output signal;

a delay circuit, operatively connected to said AND gate, for delaying the output signal from said AND gate by between one cycle and one and one-half cycle of the first clock pulse to produce a delayed signal; and

an OR gate operatively connected to receive the output signal from said AND gate, to receive the delayed signal from said delay circuit and to supply the second clock pulse to said encoding and decoding unit.

6. A system according to claim 5, wherein said one-third frequency divider comprises first and second flip-flops, having clock terminals operatively connected to said first clock pulse generating circuit to receive the first clock pulse, a first J terminal of said first flip-flop operatively connected to a negative output terminal of said first flip-flop, the positive output terminal of said second flip-flop being operatively connected to said encoding and decoding unit and said AND gate to supply the first clock pulse.

7. A system according to claim 1, wherein said encoding and decoding unit comprises:

a first shift register, having two bits, operatively connected to said second clock pulse generating circuit to receive the second clock pulse and to receive the write data;

a second shift register, having three bits, operatively connected to said first clock pulse generating circuit to receive the first clock pulse and to receive the read data; and

an encoding and decoding circuit, operatively connected to said first and second shift registers, for receiving the write data from said first shift register, for encoding the write data in accordance with the (1,7) coding to produce encoded data and for outputting the encoded data to said second shift register, when a data write operation is carried out, and for receiving the read data from said second shift register, for decoding the read data in accordance with the (1,7) decoding to produce decoded data and for outputting the decoded data to said first shift register, when a data read operation is carried out.

8. A system for modulating and demodulating data written into and from a magnetic recording medium, comprising:

reference signal means for providing a reference signal having a reference frequency;

one-third divider means for dividing the reference signal by one-third to produce a first clock pulse signal having a first frequency equal to one-third of the reference frequency;

one-half divider means for dividing the reference signal by one-half to produce a second clock pulse signal having a second frequency equal to one-half the reference frequency; and

encoding/decoding means for encoding write data to be written onto the magnetic recording medium and for decoding read data read from the magnetic recording medium, using the first and second clock pulse signals.

9. A system for modulating and demodulating data written into and read from a magnetic recording medium in accordance with a (1,7) run length limited method, the magnetic medium providing a reference signal, said system comprising:

a first clock pulse generating circuit, operatively connected to receive the reference signal from the recording medium, for generating first clock pulses having a first frequency equal to a data write frequency in accordance with a phase of the reference signal;

a second clock pulse generating circuit, operatively connected to receive the first clock pulses, for generating second clock pulses having a second frequency, the second frequency being two-thirds of the first frequency, said second clock pulse generating circuit including

a one-third frequency divider, operatively connected to said first clock pulse generating circuit to receive the first clock pulses, for producing gate pulses having a third frequency equal to one-third of the first frequency; and

an OR gate, operatively connected to said first clock pulse generating circuit to receive the first clock pulses and to said one-third frequency divider to receive the gate pulses for outputting the second clock pulses; and

an encoding and decoding unit, operatively connected to said first clock pulse generating circuit and said OR gate, for encoding write data to be written in accordance with (1,7) encoding and for decoding read data read in accordance with (1,7) decoding, in response to the first and second clock pulses.

10. A system according to claim 9, wherein said one-third frequency divider comprises first and second flip-flops, each having J, clock and positive and negative output terminals, the clock terminals operatively connected to said first clock pulse generating circuit to receive the first clock pules, the J terminal of said first flip-flop operatively connected to the positive output terminal of said second flip-flop, the negative output terminal of said first flip-flop operatively connected to the J terminal of said second flip-flop and to said encoding and decoding unit, and the positive output terminal of said second flip-flop operatively connected to said OR gate to supply the gate pulses.

11. A system for modulating and demodulating data written into and read from a magnetic recording medium in accordance with a (1,7) run length limited method, the magnetic medium providing a reference signal, said system comprising:

a first clock pulse generating circuit, operatively connected to receive the reference signal from the recording medium, for generating first clock pulses having a first frequency equal to a data write frequency in accordance with a phase of the reference signal;

a second clock pulse generating circuit, operatively connected to receive the first clock pulses, for generating second clock pulses having a second frequency, the second frequency being two-thirds of the first frequency, said second clock pulse generating circuit including

a one-third frequency divider, operatively connected to said first clock pulse generating circuit to receive the first clock pulses, for producing gate pulses having a frequency one-third that of the first frequency of the first clock pulses;

an AND gate, operatively connected to said first clock pulse generating circuit to receive the first clock pulses and to said one-third frequency divider to receive the gate pulses, for producing an output signal;

a delay circuit, operatively connected to said AND gate, for delaying the output signal from said AND gate by between one cycle and one and one-half cycle of the first clock pulses to produce a delayed signal; and

an OR gate operatively connected to receive the output signal from said AND gate and the delayed signal from said delay circuit and to output the second clock pulses; and

an encoding and decoding unit, operatively connected to said first clock pulse generating circuit and said OR gate, for encoding write data to be written in accordance with (1,7) encoding and for decoding read data read in accordance with (1,7) decoding, in response to the first and second clock pulses.

12. A system according to claim 11, wherein said one-third frequency divider comprises first and second flip-flops, each having J, clock and positive and negative output terminals, the clock terminals operatively connected to said first clock pulse generating circuit to receive the first clock pulses, the J terminal of said first flip-flop operatively connected to the positive output terminal of said second flip-flop, the negative output terminal of said first flip-flop, operatively connected to the J terminal of said second flip-flop and to said encoding and decoding unit, and the positive output terminal of said second flip-flop operatively connected to said AND gate to supply the gate pulses.

13. A system for modulating and demodulating data written into and read from a magnetic recording medium in accordance with a (1,7) run length limited method, the magnetic medium providing a reference signal, said system comprising:

a first clock pulse generating circuit, operatively connected to receive the reference signal from the recording medium, for generating first clock pulses having a first frequency equal to a data write frequency in accordance with a phase of the reference signal;

a second clock pulse generating circuit, operatively connected to receive the first clock pulses, for generating second clock pulses having a second frequency, the second frequency being two-thirds of the first frequency; and

an encoding and decoding unit, operatively connected to said first and second clock pulses generating circuits, for encoding write data to be written in accordance with (1,7) encoding and for decoding read data read in accordance with (1,7) decoding, in response to the first and second clock pulses;

said encoding and decoding unit including

a first shift register, having two bits, operatively connected to said second clock pulse generating circuit to receive the second clock pulses and to receive the write data;

a second shift register, having three bits, operatively connected to said first clock pulse generating circuit to receive the first clock pulses and to receive the read data; and

an encoding and decoding circuit, operatively connected to said first and second shift registers, for receiving the write data from said first shift register for encoding the write data in accordance with the (1,7) coding to produce encoded data and for outputting the encoded data to said second shift register, when a data write operation is carried out, and for receiving the read data from said second shift register, for decoding the read data in accordance with the (1,7) decoding to produce decoded data and for outputting the decoded data to said first shift register, when a data read operation is carried out.