Digital multiplying circuit

• US 4,866,654 A
• Filed: 02/22/1985
• Issued: 09/12/1989
• Est. Priority Date: 02/24/1984
• Status: Expired due to Fees

• Current Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Original Assignee: Hoya Corporation
• Inventors: Yamada, Yasuhiro
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Shaw, Dale M.
• Application Number:
  US06/704,635
• Time in Patent Office: 1,663 Days
• Field of Search: 364/754, 364/757, 371/37, 371/39, 371/40
• US Class Current: 708/492
• CPC Class Codes: G06F 7/724 Finite field arithmetic for error detection or correction in general H03M13/00, in computers G06F11/10

Abstract

A digital multiplying circuit comprises an input terminal serially applied with input vectors which are elements of a finite field GF(2^h), where h is a natural number, an output terminal for producing a signal obtained by multiplying a desired multiplying constant to one input vector, and h multiplying circuit parts each comprising a multiplier and a data selector for selectively producing an input or output signal of the multiplier responsive to an external selection signal. The h multiplying circuit parts are coupled in series between the input terminal and the output terminal, and an r-th multiplier among the multipliers with the h multiplying circuit parts has a multiplying constant α^z, where r=1, 2, . . . , h, α is a primitive element of the finite field GF(2^h) and z=2.sup.(r-1). At least one of the data selectors within the h multiplying circuit parts comprises a control terminal and is forced to produce a zero output signal responsive to an external control signal applied to the control terminal.

Claims

1. A digital multiplying circuit comprising:

input terminal means sequentially applied with input vectors which are elements of a finite field GF(2^h), where h is a natural number;

output terminal means for producing a signal obtained by multiplying a desired multiplying constant to one input vector; and

h multiplying circuit parts each comprising an input terminal, an output terminal, a multiplier and a data selector which has a first input terminal directly coupled to said input terminal of each multiplying circuit part, a second input terminal coupled through said multiplier to said input terminal of each multiplying circuit part, a selection terminal, and an output terminal utilized as said output terminal of each multiplying circuit part, thereby to selectively produce an input or output signal of said multiplier responsive to an external selection signal, said h multiplying circuit parts being coupled in series between said input terminal means and said output terminal means,

an r-th multiplier among the multipliers within said h multiplying circuit parts having a multiplying constant α

^z, where r=1, 2, . . . , h, α

is a primitive element of the finite field GF(2^h) and z=2.sup.(r-1),

at least one of the data selectors within said h multiplying circuit parts comprising a control terminal, said at least one data selector being forced to produce a zero output signal responsive to an external control signal applied to said control terminal.

2. A digital multiplying circuit as claimed in claim 1 in which each of the multipliers within said h multiplying circuit parts is constituted by a predetermined number of 2-input exclusive-OR circuits, said predetermined number falling within a range from a minimum of one to a maximum of hx(h-1).

3. A digital multiplying circuit as claimed in claim 1 in which said input terminal means is sequentially applied with intermediate operation vectors Q₀ through Q_n which are obtained from the following equation by use of m h-bit data vectors d₁ through d_m within a Reed Solomon code and a (n+1) row by m column matrix, ##EQU18## said data vectors d₁ through d_m being described by a row matrix [d₁ d₂ . . . d_m P₀ P₁ . . . P_n ], where P₀ through P_n represent n h-bit check vectors, m and n are natural numbers and symbols " " represent multiplications in the finite field GF(2^h), and said h multiplying circuit parts as a whole successively multiply constant vectors a₀₀ through a_nn in the following equation to each of said intermediate operation vectors Q₀ through Q_n, ##EQU19## where symbols "⊕

" represent additions in the finite field GF(2^h).

4. A digital multiplying circuit as claimed in claim 1 in which said at least one data selector comprising said control terminal is forced to produce a zero output signal responsive to said external control signal when said desired multiplying constant is equal to zero.