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Multiple memory loading system based on multilevel lists

  • US 4,866,668 A
  • Filed: 03/30/1988
  • Issued: 09/12/1989
  • Est. Priority Date: 06/01/1984
  • Status: Expired due to Fees
First Claim
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1. A method of loading n intercoupled processing modules of a digital switching network having a unique network address for each such intercoupled processing module with each of m different generic load segment data blocks into the random access program control memories of m corresponding predetermined subsets of said n intercoupled processing modules, said method comprising the steps of:

  • establishing the ordinal sequence in which said m different generic load segment data blocks are to be loaded,creating m initial lists, each corresponding to a respective different one of said m data blocks, for determining the network addresses and the serial and parallel loading sequence in which the program control memories of the corresponding processing modules are to be loaded in pyramidal fashion with each said respective different one data block, andin accordance with the first initial list, transmitting in parallel the first generic load segment data block to each of a corresponding plurality of first-level processing modules and loading the respective program memory of each such first-level module with said first generic load segment data block, said first data block being transmitted to all said corresponding first-level modules together with primary sublist data derived from said first initial list for establishing a respective primary sublist for determining the network addresses and loading sequence for transmitting and loading said first generic load segment data block from each corresponding first-level module'"'"'s respective program control memory into the program control memories of a respective plurality of second-level and any further-level processing modules to be loaded with said first generic load segment data block, then concurrentlyin accordance with the corresponding respective primary sublist concurrently transmitting in parallel said first data block from the respective program control memory of each of said first-level processing modules and loading said first data block into the memories of the respective second-level processing modules, said first data block being transmitted to all said corresponding second-level modules together with secondary sublist data derived from the corresponding primary sublist for establishing any required secondary sublist for determining the network addresses and loading sequence for transmitting and loading said first data block into the program control memories of any further-level processing modules from the respective program control memories of each of the second-level processing modules, andin accordance with a second initial list, said second initial list being different from said first initial list, trasmitting in parallel the second generic load segment data block to each of the first-level processing modules designated by said second initial list and loading the respective program memory of each such first-level module with said second data block, said second data block being transmitted to all said corresponding first-level processing modules together with primary sublist data derived from said second initial list for determining the network addresses and loading sequence for transmitting and loading said second data block from each designated first-level module'"'"'s respective program control memory into the program control memories of a respective plurality of second-level and any further-level processing modules to be loaded with said second generic load segment data.

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