Multiple memory loading system based on multilevel lists

• US 4,866,668 A
• Filed: 03/30/1988
• Issued: 09/12/1989
• Est. Priority Date: 06/01/1984
• Status: Expired due to Fees

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: Alcatel NV (Nokia Corporation)
• Inventors: Donegan, Anthony, Edmonds, Mark P.
• Primary Examiner(s): Anderson, Lawrence E.
• Application Number:
  US07/178,887
• Time in Patent Office: 531 Days
• Field of Search: 340/825.02, 370/94, 370/60, 364/200 MS File, 364/900 MS File, 364/300
• US Class Current: 711/148
• CPC Class Codes: G06F 15/17393 having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

A multiple memory loading system with a plurality of intercoupled modules including memories able to transmit each of a plurality of data packets to the memories of a number of modules wherein said data packet may then be stored. The transmission of each of the data packets from one module only occurs to the memories of a number of predetermined modules of an initial set and indirectly from said memories to memories of other modules.

Claims

1. A method of loading n intercoupled processing modules of a digital switching network having a unique network address for each such intercoupled processing module with each of m different generic load segment data blocks into the random access program control memories of m corresponding predetermined subsets of said n intercoupled processing modules, said method comprising the steps of:

establishing the ordinal sequence in which said m different generic load segment data blocks are to be loaded,

creating m initial lists, each corresponding to a respective different one of said m data blocks, for determining the network addresses and the serial and parallel loading sequence in which the program control memories of the corresponding processing modules are to be loaded in pyramidal fashion with each said respective different one data block, and

in accordance with the first initial list, transmitting in parallel the first generic load segment data block to each of a corresponding plurality of first-level processing modules and loading the respective program memory of each such first-level module with said first generic load segment data block, said first data block being transmitted to all said corresponding first-level modules together with primary sublist data derived from said first initial list for establishing a respective primary sublist for determining the network addresses and loading sequence for transmitting and loading said first generic load segment data block from each corresponding first-level module'"'"'s respective program control memory into the program control memories of a respective plurality of second-level and any further-level processing modules to be loaded with said first generic load segment data block, then concurrently

in accordance with the corresponding respective primary sublist concurrently transmitting in parallel said first data block from the respective program control memory of each of said first-level processing modules and loading said first data block into the memories of the respective second-level processing modules, said first data block being transmitted to all said corresponding second-level modules together with secondary sublist data derived from the corresponding primary sublist for establishing any required secondary sublist for determining the network addresses and loading sequence for transmitting and loading said first data block into the program control memories of any further-level processing modules from the respective program control memories of each of the second-level processing modules, and

in accordance with a second initial list, said second initial list being different from said first initial list, trasmitting in parallel the second generic load segment data block to each of the first-level processing modules designated by said second initial list and loading the respective program memory of each such first-level module with said second data block, said second data block being transmitted to all said corresponding first-level processing modules together with primary sublist data derived from said second initial list for determining the network addresses and loading sequence for transmitting and loading said second data block from each designated first-level module'"'"'s respective program control memory into the program control memories of a respective plurality of second-level and any further-level processing modules to be loaded with said second generic load segment data.

2. The loading method of claim 1, wherein

said plurality of generic load segment data blocks are arranged in a controllist in such a way that the number of iterative steps required to load these generic load segment data blocks in the modules of respective initial sets decreases from top to bottom of said list,

at least two successive generic load segment data blocks of said list, starting at the top thereof, are concurrently transmitted in rotation by corresponding ones of at least two respective initialization modules, to the first-level modules of respective initial lists and

after any of said initialization modules has finished the loading of all its corresponding generic load segment data blocks into the first-level modules of said respective initial lists, it attempts to load the generic load segment data blocks normally loaded by another of said initialization modules.

3. The loading method of claim 1, wherein

each of the processing modules is coupled to said digital switching network via time division multiplex links comprising a plurality of time channels and the general load segment data block is transmitted to a predetermined subset of processing modules simultaneously on a plurality of said channels, together with a parameter indicating the maximum number of channels which may be used by said predetermined module for the transmission of said generic load segment data block to each of other predetermined modules.

4. The loading method of claim 1, further comprising the step of:

subdividing said initial list into a maximum number of sublists equal to the maximum number of first-level processing modules to which said first generic load segment data block is to be simultaneously transmitted, each such sublist including the network address of a corresponding one of said first-level processing modules, to thereby form said primary sublists.

5. The loading method of claim 1, further comprising the step of:

subdividing each said respective primary sublist into a maximum number of secondary sublists equal to one plus the maximum number of processing modules to which said first generic load segment data block is to be simultaneously transmitted from said respective memory, whereby a particular previously loaded first-level module, after it has loaded said maximum number of second-level modules associated with said secondary sublists, may thereafter itself load one or more third-level modules in accordance with the remaining said secondary sublists concurrently with the loading of other third-level modules from said second-level modules, thereby further speeding up the loading process.

6. The loading method of claim 5, further comprising the steps of

transmitting said first data block to predetermined second-level modules of the sublists which do not include said previously loaded first-level module and

thereafter transmitting from said previously loaded first-level module said data block directly to predetermined third-level modules of the sublist of which it forms part.

7. The loading method of claim 1, wherein

said modules are intercoupled through a multi-stage digital switching network,

said modules each have an address which comprises a number of digits equal to the number of stages of said network and which is able to control path set up in respective ones of said stages and

in each of said initial lists and said sublists the modules thereof are ordered according to their network addresses.

8. The loading method of claim 7, wherein

said network addresses of the modules to be successively loaded with a given generic load segment are ordered in a decreasing network address order, with the first modules on any given initial list or given sublist being the first to be loaded and with each sublist associated therewith being a contiguous portion of said given initial list or given sublist,

whereby a relatively large path length will result between the different first-level modules and also between the modules on different primary sublists, and whereby, as the number of modules concurrently involved in the loading process increases, the average path length from a module then transmitting the generic load segment data to the moduls then being loaded therewith decreases.

9. The loading method of claim 1, wherein

said initial list is transmitted to each first-level module and the modules initially loaded from said each first-level module together with a first set of parameters indicating the maximum number of lower-level modules to be simultaneously loaded from a higher-level module and the total number of modules to be directly or indirectly laded from the receiving module in successive levels of a cascaded initial loading operation, from which the lists and sublists associated with subsequent initial loading operations from said each module may be derived, as well as a further parameter from which may be derived from said initial list other primary sublists associated with initial loading operations from other said first-level modules, and

after its memory has been loaded, each module on a given said primary sublist uses said further parameter to derive all the other said primary sublists from said initial list and attempts during an additional memory loading operation to load said generic load segment data block into any homologous module of each of these other sublists.

10. The loading method of claim 9, wherein at least two of said primary sublists have a same length larger than the length of the other primary sublists, whereby each said module will load a corresponding said homologous module on at least one of said primary sublists.

11. The loading method of claim 9, wherein the memory of each of said modules to be loaded stores a phase indicator which is set to a first predetermined condition when the memory has been loaded with its corresponding generic load segment data block to thereby prevent a renewed loading of said memory during said additional memory operation.

12. The loading method of claim 10, wherein all but at most one of said primary sublists have said larger length, whereby each said module on a given primary list will have corresponding said homologous modules on all but at most one of the other said primary sublists.