Testing arrangement for a DRAM with redundancy

• US 4,866,676 A
• Filed: 03/24/1988
• Issued: 09/12/1989
• Est. Priority Date: 03/24/1988
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Watkins, George G., Hoekstra, George P., Crisp, Richard D.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Gossage, Glenn A.
• Application Number:
  US07/172,514
• Time in Patent Office: 537 Days
• Field of Search: 365/200, 365/201, 365/51, 365/63, 371/10, 371/21
• US Class Current: 365/200
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/78 using programmable devices

Abstract

A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.

Claims

1. A memory having a read mode and a write mode, comprising:

a normal array of memory cells located at intersections of word lines and bit lines, said bit lines arranged in a plurality of bit line pairs each having one of a first and a second true/complement orientation, each bit line pair characterized as having an address and as developing a voltage differential of a polarity representative of one of first and second logic states;

decoder means for selectively coupling a selected bit line pair from the plurality of bit line pairs to a data line pair in response to a plurality of address signals, a particular combination of address signals being the address of a particular bit line pair, whereby the selected bit line pair and the data line pair to which the selected bit line pair is coupled both have a voltage differential of the same polarity and representative of the same logic state;

a redundant column having a redundant bit line pair of the first true/complement orientation for replacing a defective bit line pair of the plurality of bit line pairs;

redundant decoder means for coupling the redundant bit line pair to the data line pair in response to the address of the defective bit line pair;

detection means for providing an invert signal at the first logic state if the defective bit line pair has a different true/complement orientation than that of the redundant bit line pair and at the second logic state if the defective bit line pair has the same true/complement orientation as that of the redundant bit line pair;

output means for receiving the invert signal and providing an output signal at the logic state which is the same as that present on the data line pair when the memory is in the read mode and the detection means has provided the inert signal at the second logic state and for providing the output signal at the logic state which is opposite to that present on the data line pair when the memory in the read mode and the detection means has provided the invert signal at the first logic state; and

input means for providing the voltage differential onto other the data line pair representative of the logic state of an input signal when the memory is in the write mode and the detection means has provided the invert signal at the second logic state and for providing the voltage differential onto the data line pair representative of the logic state opposite to that of the logic state of the input signal when the memory is in the write mode and the detection means has provided the invert signal at the first logic state.

2. The memory of claim 1 wherein the bit line pairs at an odd address are characterized as having the first true/complement orientation and the bit line pairs at an even address are characterized as having the second true/complement orientation.

3. The memory of claim 2, wherein the detection means comprises:

redundancy detection means for providing a redundancy signal if the plurality of address signals is the address of the defective bit line pair; and

odd/even detector means, coupled to the redundancy detection means, for providing the invert signal at the first logic state if the redundancy detection means provides the redundancy signal and the address is odd.

4. A DRAM having an array of bit line pairs characterized as having one of a first and a second true/complement orientation, each bit line pair having an address which selects the particular bit line pair having the address wherein data is transferred between the bit line pair selected by the particular address and a data line pair, comprising:

input/output means, coupled to the data line pair for writing external input data onto the data line pair in a write mode and for providing external output data from the data line pair in the read mode;

a redundant bit line pair of the first true/complement orientation;

redundancy means, coupled to the redundant bit line pair, for substituting the redundant bit line pair for a defective one of the bit line pairs;

input/output control means, coupled to the input/output means, for inverting the external input data written onto the data line pair in the write mode and inverting the external output data provided from the data line pair in the read mode if the address is for the defective bit line pair and the defective bit line pair is of the second true/complement orientation.

5. In a DRAM having an array of bit line pairs characterized as having one of a first and second true/complement orientation, each bit line pair having an address which selects the particular bit line pair having the address wherein data is transferred between the bit line pair selected by the particular address and a data line pair, an input/output circuit for writing external input data onto the data line pair in the read mode, and for providing external output data from the data line pair in the read mode, and a redundant bit line pair of the first true/complement orientation, a method for implementing redundancy, comprising the steps of:

substituting the redundant bit line pair for a defective one of the array of bit line pairs; and

inverting the external input data written onto the data line pair in the write mode and inverting the external output data from the data line pair in the read mode if the address is for the defective bit line pair and the defective bit line pair is of the second true/complement orientation.