Packet switch with dynamic allocation of inputs

• US 4,866,701 A
• Filed: 09/02/1988
• Issued: 09/12/1989
• Est. Priority Date: 09/02/1988
• Status: Expired due to Term

• Current Assignee: TTI Inventions A LLC (Intellectual Ventures LLC)
• Original Assignee: Bell Communications Research, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Sincoskie, Walter D., Giacopelli, James N.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Marcelo, Melvin
• Application Number:
  US07/240,745
• Time in Patent Office: 375 Days
• Field of Search: 370/54, 370/60, 370/94, 370/55, 370/58, 370/65
• US Class Current: 370/411
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/561 Star, e.g. cross-connect, concentrator, subscriber group equipment, remote electronics
• CPC Class Codes: H04L 2012/5631 Resource management and allocation
• CPC Class Codes: H04L 2012/5649 Cell delay or jitter
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 49/106 using space switching, e.g. crossbar or matrix
• CPC Class Codes: H04L 49/1561 Distribute and route fabrics, e.g. Batcher-Banyan
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/258 Grouping

Abstract

A novel packet switch architecture is disclosed. In the novel packet switch, inputs are dynamically allocated between newly arriving and recirculating packets to make maximum use of available bandwidth while simultaneously resolving output port conflicts.

Claims

1. A recirculation arrangement for use in a packet switch having a plurality of inputs and a plurality of outputs, said recirculation arrangement serving to route data packets which cannot be routed to said outputs back to said inputs, said recirculation arrangement comprising

means for generating steering packets containing input addresses,

means for combining said steering packets and said data packets to be routed back to said inputs so that said addresses in said steering packets form headers for said data packets to be routed back to said inputs, and

a self-routing network for routing said data packets to said inputs based on said headers.

2. The arrangement of claim 1 wherein said routing network is a banyan network and said recirculation arrangement further includes a concentrator network for concentrating said steering packets before they are combined with said data packets.

3. A packet switch comprising

a plurality of input port controllers for receiving newly arriving and recirculating data packets synchronously in time slots,

a plurality of output port controllers,

conflict resolving means for resolving conflicts among data packets containing the same destination address so as to indicate which packets are to be routed to said output port controllers so that they can exit from said switch and to indicate which packets are to be recirculated to said input port controllers,

routing means for routing packets indicated as exiting by said conflict resolution means to said output port controllers, and

recirculating means for recirculating packets indicated as recirculating by said conflict resolution means back to said input port controllers,

said recirculating means serving to allocate said input port controllers between said newly arriving packets and said recirculating packets on a slot-by-slot basis.

4. The switch of claim 3 wherein said conflict resolution means comprises a trap network.

5. The switch of claim 3 wherein said routing means comprises a banyan network.

6. The switch of claim 3 wherein said routing means comprises a plurality of routing networks to provide multiple paths to each output port controller.

7. The switch of claim 3 wherein said recirculating means comprises means for combining said recirculating packets with steering packets to provide said recirculating packets with headers containing the addresses of input port controllers and routing means for routing said recirculating packets to the input port controllers indicated by the headers.

8. A packet switch for synchronously routing data packets in time slots between a plurality of inputs and a plurality of outputs, said switch comprising:

means for resolving conflicts among data packets occupying the same time slot and containing the same output address to indicate which of said packets is to be recirculated to said inputs and which of said packets is to be routed to said outputs, and

recirculating means for allocating said inputs on a slot-by-slot basis between newly arriving data packets and recirculating packets to enable said recirculating packets to be routed back to said inputs.

9. The switch of claim 8 wherein said address is a logical address or a physical address.

10. A method for synchronously routing data packets in time slots between a plurality of inputs and a plurality of outputs of a packet switch comprising the steps of:

resolving conflicts among data packets occupying the same time slot and containing the same output address to indicate which of said packets is to be recirculated to said inputs and which of said packets is to be routed to said outputs, and

allocating said inputs on a slot-by-slot basis between newly arriving data packets and recirculating data packets to enable said recirculating packets to be routed back to said inputs.

11. The method of claim 10 wherein said method further comprises the step of delaying each newly arriving data packet at an input for a duration in excess of one time slot.

12. A method for routing packets in a packet switch comprising the steps of:

determining whether each of a plurality of inputs of said switch will submit a newly arriving data packet to said switch in a particular subsequent time slot,

generating a steering packet at each input that will not submit a newly arriving data packet to said switch in said subsequent time slot, said steering packets containing the addresses of the inputs issuing them,

combining said steering packets with recirculating data packets to provide said recirculating packets with the addresses of inputs that will not submit a newly arriving packet in said subsequent time slot, and

routing said recirculating packets to the inputs indicated by said addresses so that said recirculating packets can be resubmitted to said switch in said subsequent time slot.