Operational function checking method and device for microprocessors

• US 4,866,713 A
• Filed: 11/02/1987
• Issued: 09/12/1989
• Est. Priority Date: 11/02/1987
• Status: Expired due to Term

• Current Assignee: General Dynamics C4 Systems Incorporated (General Dynamics Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Worger, William R., Piosenka, Gerald V.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US07/115,483
• Time in Patent Office: 680 Days
• Field of Search: 371/38, 371/51, 371/62, 371/16
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Abstract

An operational function checking method and device for a microprocessor, which uses four circuits to verify that a microprocessor and processing system are operating properly.

Claims

1. An operational function checking device for a microprocessor comprising:

an error logic circuit;

a parallel CRC having first and second inputs and an output said output of said parallel CRC coupled to said error logic circuit;

an address bus of said microprocessor coupled to said first input of said parallel CRC;

a data bus of said microprocessor coupled to said second input of said parallel CRC;

a simple watchdog timer having an input and an output, said input coupled to a clock bus of said microprocessor, and said output coupled to said error logic circuit;

an exact time watchdog timer having an input and an output, said input being coupled to said clock bus and said output being coupled to said error logic circuit; and

a parity checker circuit with an input and an output, said input coupled to said address bus, said data bus, and said clock bus of said microprocessor and said output being coupled to said error logic circuit.

2. An operational function checking device as claimed in claim 1 wherein said parallel CRC futher comprises:

a parallel CRC generator coupled to said data bus and said address bus, and an output;

an expected result register coupled to said address bus and data bus, and said expected result register including an output; and

a comparator having first and second inputs coupled to said outputs of said parallel CRC generator and said expected result register, respectively, and having an output coupled to said error logic circuit.

3. An operational function checking device as claimed in claim 2 wherein said parity checker circuit further comprises:

a parity checker having first and second inputs and an output, said data bus of said microprocessor coupled to said first input, said second input coupled to said clock bus, and said error logic circuit coupled to said output; and

a parity memory having an input and an output, said address bus from said microprocessor coupled to said input and said second input of said parity checker coupled to said output.

4. An operational function checking device for a microprocessor comprising:

an error logic circuit;

a control circuit coupled to an address bus and a data bus of said microprocessor and having first, second, and third outputs;

a parallel CRC having first and second inputs each coupled to one of said data bus and said address bus, a third input coupled to said first output of said control circuit, a fourth input, and an output coupled to said error logic circuit;

a simple watchdog timer having a first input coupled to said microprocessor, a second input coupled to said second output of said control circuit, and an output coupled to said error logic circuit;

an exact time watchdog timer having a first input adapted to receive a clock input from said microprocessor, a second input coupled to said first output of said control circuit, a third input coupled to said third output of said control circuit, a first output coupled to the fourth input of said parallel CRC, and a second output coupled to said error logic circuit;

a parity checker having a first input coupled to said data bus from said microprocessor, a second input, and an output coupled to said error logic means; and

a parity memory having an input coupled to said address bus of said microprocessor, and an output coupled to said second input of said parity checker.

5. An operational function checking method for a microprocessor comprising the steps of:

providing a microprocessor;

accumulating a cyclic redundancy check for data and addresses from said microprocessor over a given number of process cycles;

comparing accumulated CRC from said accumulating step with stored data;

signaling an error if said accumulated CRC and said stored data do not watch;

starting a simple watchdog timer;

sending a reset signal from said microprocessor to said simple watchdog timer before the counter reaches zero;

signaling an error if said reset signal is not sent before the counter reaches zero;

starting an exact time watchdog timer at the beginning of a processor operation, and counting each instruction cycle of said microprocessor

stopping said exact time watchdog timer at a predetermined count;

sending a stop signal to said exact time watchdog timer from said microprocessor at substantially the same time the exact time watchdog timer stops;

signaling an error if said stop signal and the stopping of said count do not coincide;

appending a parity bit to memory which contains programs executed by the microprocessor;

programming the contents of the parity ROM so that the parity for each instruction contained in the program ROM have a predetermined parity; and

signaling an error if a parity not equal to said predetermined parity is detected.

6. An operational function checking device for a microprocessor comprising:

CRC (cyclic redundancy checker) means coupled to the microprocessor to receive data, address, and clock information from said microprocessor;

simple watchdog timer means for checking a frequency of occurance of a reset signal from the microprocessor;

exact time watchdog timer means for checking a length of time required by the microprocessor for executing a given sequence of information;

parity check means;

error circuit means coupled to said CRC means, said simple watchdog timer means, said exact time watchdog timer means, and said parity means to receive an error signal from said simpled watchdog timer means, said exact timer watchdog timer means, and said parity means;

said error circuit means for signalling a microprocessor error when an error signal is received from at least one of said CRC means, said simple watchdog timer means, said exact time watchdog timer means, or said parity means;

said simple watchdog timer means and said exact time watchdog timer means coupled to the microprocessor to receive said clock information;

said parity check means coupled to the microprocessor to receive said data, address, and clock information from the microprocessor; and

said exact time watchdog timer means coupled to said CRC means to relay an end of information sequence signal to said CRC means.

7. An operational function checking device for a microprocessor according to claim 6 wherein the operational function checking device further comprises a control circuit means for controlling the operation of the operational function checking device.

8. An operational function checking device for a microprocessor according to claim 6 wherein said CRC means comprises:

CRC generator means coupled to the microprocessor to receive said data, address, and clock information;

said CRC generator means for determining an information pattern from said received data;

expected results means for storing a predetermined information pattern;

comparitor means coupled to said CRC generator means to receive said information patten from said CRC generator means, and further coupled to said expected results means for receiving said predetermined information pattern from said expected results means;

said comparitor means for comparing said predetermined information patten with said received information pattern to determine whether an error has occured; and

said comparitor means coupled to said error circuit means.