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Operational function checking method and device for microprocessors

  • US 4,866,713 A
  • Filed: 11/02/1987
  • Issued: 09/12/1989
  • Est. Priority Date: 11/02/1987
  • Status: Expired due to Term
First Claim
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1. An operational function checking device for a microprocessor comprising:

  • an error logic circuit;

    a parallel CRC having first and second inputs and an output said output of said parallel CRC coupled to said error logic circuit;

    an address bus of said microprocessor coupled to said first input of said parallel CRC;

    a data bus of said microprocessor coupled to said second input of said parallel CRC;

    a simple watchdog timer having an input and an output, said input coupled to a clock bus of said microprocessor, and said output coupled to said error logic circuit;

    an exact time watchdog timer having an input and an output, said input being coupled to said clock bus and said output being coupled to said error logic circuit; and

    a parity checker circuit with an input and an output, said input coupled to said address bus, said data bus, and said clock bus of said microprocessor and said output being coupled to said error logic circuit.

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