Self-correcting digitally controlled timing circuit

• US 4,868,430 A
• Filed: 02/11/1988
• Issued: 09/19/1989
• Est. Priority Date: 02/11/1988
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: NCR Corporation
• Inventors: Stewart, John W.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US07/154,768
• Time in Patent Office: 586 Days
• Field of Search: 307/271, 307/269, 307/602, 307/597, 328/155, 328/72, 328/55, 377/20, 377/45
• US Class Current: 327/279
• CPC Class Codes: H03K 2005/0011 using a separate time interval to calibrate the delay
• CPC Class Codes: H03K 2005/00234 using circuits having two logic levels
• CPC Class Codes: H03K 2005/00241 using shift registers
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

A digitally controlled timing circuit for providing an output pulse signal precisely delayed with respect to an input signal irrespective of the time of occurrence of a system clock, but which uses the precision of the system clock to self-correct any inaccuracy in the delay includes a plurality of delay elements, the delay period of a respective one of which is adjustable, coupled between an input terminal, to which an input terminal is applied, and an output terminal, from which a delayed output signal is to be derived. Coupled to the input terminal and the plurality of delay elements is a toggled flip-flop which, with the delay elements, during a calibrate mode, forms an adjustable oscillator and generates a sequence of signals the lapse of time between successive ones of which is established by delays imparted by selected ones of the delay elements. The delays imparted by selected ones of the delay elements. The output of the flip-flop is coupled to a shift register/counter which is used to measure the length of time required for the flip-flop to generate a prescribed number of signals after its receipt of an input signal. Upon counting a prescribed number of signals generated by the flip-flop the shift register/counter delivers an output signal to a comparator, which compares the length of time measured by the shift register/counter with a reference length of time. Depending upon the comparison, an up/down counter is incremented or decremented. Decoded contents of the counter are used to adjust the delay elements.

Claims

1. A circuit for producing an output signal the time of occurrence of which is delayed with respect to an input signal applied thereto comprising:

first means, responsive to an input signal, for generating a sequence of first signals;

counter means coupled to said first means for counting successive ones of said first signals and generating a second signal upon counting a preselected number of said first signals to measure the length of time required for said first means to generate a prescribed number of said first signals after receipt of an input signal by said first means;

control means, coupled to said first means, for controllably adjusting and setting the lapse of time between successive ones of said first signals in accordance with the time of occurrence of said second signal relative to a sequence of periodically occurring signals the lapse of time between successive ones of which corresponds to said reference length of time applied to said first means as an input signal; and

second means for producing an output signal delayed with respect to an input signal in accordance with the lapse of time between successive ones of said first signals.

2. A circuit according to claim 1, wherein said control means comprises an up/down counter the contents of which are controllably incremented or decremented in accordance with whether the length of time between a respective one of said periodically occurring signals and said second signal exceeds the length of time between successive ones of said periodically occurring signals.

3. A circuit according to claim 2, wherein said first means comprises a plurality of cascaded delay elements, the delay period of a respective one of which is adjustable, to which said first signals are coupled for setting the lapse of time between successive ones of which, and said control means includes means for controllably adjusting the delay of each of said delay elements in accordance with the contents of each of said delay elements in accordance with the contents of said up/down counter.

4. A circuit for producing an output signal the time of occurrence of which is delayed with respect to an input signal applied thereto comprising:

first means, responsive to an input signal, for generating a sequence of first signals and including adjustable delay means for controllably adjusting the lapse of time between successive ones of said first signals;

second means, coupled to said first means, for producing an output signal in response to said first means generating a prescribed number of said first signals after receipt of an input signal by said first means; and

third means, coupled to said first and second means, for controllably adjusting the lapse of time between successive ones of said first signals in accordance with a prescribed relationship between the length of time elapsed between an input signal and the production of an output signal by said second means and a reference length of time;

said third means includes means, coupled to receive said input signal and said output signal, for generating a second signal representative of whether or not said output signal is generated by said second means prior to receipt of a further input signal by said first means.

5. A circuit according to claim 4, further including fourth means, coupled to said adjustable delay means and coupled to receive said input signal, for selectively generating a delay signal corresponding to a version of said input signal delayed by a time interval produced by a selected portion of said adjustable delay means.

6. A circuit according to claim 4, wherein said third means comprises control means for controllably adjusting the lapse of time between successive ones of said first signals in accordance with the time of occurrence of said output signal relative to a reference signal applied to said first means as an input signal.

7. A circuit according to claim 6, wherein said reference signal comprises a sequence of periodically occurring signals the lapse of time between successive ones of which corresponds to said reference length of time.

8. A circuit according to claim 7, wherein said third means comprises an up/down counter the contents of which are controllably incremented or decremented in accordance with whether the length of time between a respective one of said periodically occurring signals and said output signal exceeds the length of time between successive ones of said periodically occurring signals.

9. A circuit according to claim 7, wherein said first means comprises a plurality of cascaded delay elements, the delay period of a respective one of which is adjustable, to which said first signals are coupled for setting the lapse of time between successive ones of which, and said third means comprises means for controllably adjusting the delay of each of said delay elements in accordance with the contents of said up/down counter.

10. A circuit for producing an output signal the time of occurrence of which is delayed with respect to an input signal applied thereto comprising:

an input terminal to which an input signal is applied;

an output terminal from which an output signal corresponding to a delayed version of said input signal is to be derived;

a plurality of delay elements, the delay period of a respective one of which is adjustable, coupled between said input terminal and said output terminal;

first means, coupled to said input terminal and said plurality of delay elements, for generating a sequence of first signals the lapse of time between successive ones of which is established by delays imparted by elements of said plurality;

second means, coupled to said first means, for measuring the length of time required for said first means to generate a prescribed number of said first signals after receipt of an input signal by said first means;

third means, coupled to said plurality of delay elements, for controllably setting the delay periods thereof; and

an up/down counter the contents of which are controllably incremented or decremented in accordance with whether the length of time between a respective one of said periodically occurring signals and said second signal exceeds the length of time between successive ones of said periodically occurring signal, coupled to said second and third means, for controllably adjusting the delay period of each of said delay elements in accordance with a prescribed relationship between the length of time measured by said second means and a reference length of time.

11. A circuit according to claim 10, wherein said second means comprises counter means for counting successive ones of said first signals and generating a second signal upon counting a preselected number of said first signals.

12. A circuit according to claim 11, wherein said up/down counter includes means, coupled to receive said input signals and said second signal, for generating a third signal representative of whether or not said second signal is generated by said second means prior to receipt of a further input signal by said first means.

13. A circuit according to claim 11, further comprising control means connected to said up/down counter for controllably adjusting the delay periods of each of said delay elements in accordance with the time of occurrence of said second signal relative to a reference signal applied to said first means as an input signal.

14. A circuit according to claim 13, wherein said reference signal comprises a sequence of periodically occurring signals the lapse of time between successive ones of which corresponds to said reference length of time.

15. A circuit according to claim 10, further comprising decoder means coupled between stages of said up/down counter and said third means for controllably adjusting the delay of each of said delay elements in accordance with the contents of said up/down counter.

16. A circuit for producing an output signal the time of occurrence of which is delayed with respect to an input signal applied thereto comprising:

an input terminal to which an input signal is applied;

a first flip-flop having a first input for setting said flip-flop to a first state connected to said input terminal;

said first flip-flop having a non-inverted output terminal and an inverted output terminal;

a first delay device having an input terminal connected to said non-inverted output terminal for receiving a signal therefrom and an output terminal connected to a second input terminal of said first flip-flop for resetting said flip-flop;

a second flip-flop having a first input terminal for setting said second flip-flop connected to said non-inverting output terminal;

a second delay device having an input terminal connected to an inverting output terminal of said second flip-flop for receiving a signal therefrom and an output terminal connected to a second input of said second flip-flop for resetting said second flip-flop;

a third delay device having an input terminal connected to a non-inverting output terminal of said second flip-flop for receiving a signal therefrom and an output terminal connected to a third input of said second flip-flop for setting said second flip-flop; and

shift register means having a data input terminal connected to a fixed logic level and a shift input terminal connected to said inverted output terminal of said second flip-flop for shifting said fixed logic level from said input terminal to an output terminal thereof;

whereby said input signal sets said first flip-flop and an output signal of said first delay device resets said first flip-flop after a first preselected delay, said second flip-flop is set by an output signal on said inverted output terminal of said first flip-flop by a resetting thereof, said second delay device resets said second flip-flop after a second preselected delay, said third delay device sets said second flip-flop in response to a resetting thereof after a third preselected delay, which forms a self perpetuating oscillator having a preselected cycle time, and said shift register means shifts said fixed logic level by a multiple of said preselected cycle time to said output terminal thereof thereby delaying the output of said fixed logic level output by said multiple of preselected cycle times.

17. The circuit for producing an output signal the time of occurrence of which is delayed with respect to the input signal applied thereto, according to claim 16, further comprising a comparator means for comparing an arrival of a second input signal with respect to an arrival of the output signal of said shift register which is delayed with respect to said input signal thereto.