Circuit arrangement for converting digital sound-signal values into an analog sound signal

• US 4,868,572 A
• Filed: 02/29/1988
• Issued: 09/19/1989
• Est. Priority Date: 02/28/1987
• Status: Expired due to Fees

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: Alcatel NV (Nokia Corporation)
• Inventors: Reiber, Hans
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Hoff, Marc S.
• Application Number:
  US07/162,221
• Time in Patent Office: 568 Days
• Field of Search: 341/144, 341/145, 341/146, 341/154
• US Class Current: 341/145
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004
• CPC Class Codes: H03M 7/3026 the quantiser being a multiple bit one
• CPC Class Codes: H03M 7/3042 the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only

Abstract

This circuit arrangement includes an interpolation filter (3) which converts the incoming signal values (A) into interpolated signal values (B) of increased repetition frequency. The interpolated signal values (B) are reduced in word length by means of a quantizer (4a) and by quantization error feedback through an error filter (25). A D/A converter (6) consists of two or more nonweighted switching stages connected in parallel. The activated switching stages deliver currents which are added together at the output end. The D/A converter (6) is controlled by a control circuit (5) which processes the output signals (D) of the quantizer (4a). The activated switching stages are continuously interchanged on a cyclic basis, so that relative resistance tolerances in the circuit average out.

Claims

1. Circuit arrangement for converting digital sound-signal values into an analog sound signal which has the following features:

an interpolation filter in which the incoming signal values are converted into a sequence of interpolated signal values of an increased repetition rate,

a reduction circuit which reduces the word length of said interpolated signal values and includes a quantizer, an error filter, and an adding stage,

a digital-to-analog converter including a plurality of switching stages whose output currents are added at the output end of said digital-to-analog converter,

a control circuit which, in response to digital signal values at the output of said quantizer, controls said switching stages in such a way that the sum of the output currents is equal to said applied signal values, and selects respective ones of said switching stages by cyclic step-by-step switching, and

a low-pass filter following said digital-to-analog converter which delivers the analog signal.

2. A circuit arrangement as claimed in claim 1, in which the digital-to-analog converter contains at least two of said switching stages, so that it delivers pulses with at least three different amplitude values.

3. A circuit arrangement as claimed in claim 1, in which the output currents of said switching stages are added at a summing point.

4. A circuit arrangement as claimed in claim 3, in which each of said switching stages includes a resistor and a switch which, if activated, connects said resistor to the inverting input of an operational amplifier with feedback, each said resistor being connected in parallel and having the same value of resistance.

5. As circuit arrangement as claimed in claim 3, in which each of said switching stages includes a current source and a switch which, when activated, connects said current source to the inverting input of an operational amplifier with feedback, each of said current sources being substantially identical to one other.

6. A circuit arrangement as claimed in claim 5, characterized in that all current sources are controllable with a reference voltage.

7. A circuit arrangement as claimed in claim 1, in which the control circuit comprises:

an accumulator consisting of an adder having the word length of the incoming digital values and followed by a delay element, and

a read-only memory whose addresses are formed by the incoming signal values and the output values of the accumulator, and whose output data control the switching stages by switching them cyclically step by step.

8. A circuit arrangement as claimed in claim 1, in which the control circuit comprises:

a first decoder which converts the incoming digital signal values (n-bit words) into an m-out-of-2ⁿ code,

a second decoder which converts the incoming digital signal values, summed in an accumulator, into a 1-out-of-2ⁿ code, and

2ⁿ switch assemblies which are controlled by the outputs of the second decoder and, in the ON state, connect the outputs of the first decoder to other switching stages.

9. A circuit arrangement as claimed in claim 1, in which the control circuit comprises:

a decoder which converts the incoming signal values into an m-out-of-2ⁿ code,

a shift register used as a ring counter which is set by the outputs of the decoder,

an accumulator which sums the incoming signal values and delays them by one clock cycle,

an (n+1)-bit counter and an AND gate which convert the parallel output values from the accumulator into serial shift pulses for the shift register,

a register into which the information shifted out of the shift register is entered and whose outputs control the switching stages of the digital-to-analog converter, and

a reset input via which all cells of the shift register are reset to zero before a new digital signal value is transferred into the shift register in parallel.

10. A circuit arrangement as claimed in claim 1, comprising an additional reduction circuit in which each incoming signal value is converted into a number of r digital partial values whose sum is equal to said signal value and which are fed to said control circuit.

11. A circuit arrangement as claimed in claim 10, in which said partial values and the positions of said partial values are so chosen that the noise spectrum caused by their time error has a minimum in the audible range.

12. A circuit arrangement as claimed in claim 10, comprising a read-only memory to which the incoming signal values are fed as a first address,

to which the count of a cycle counter is fed as a second address, and whose data outputs are connected to the inputs of the control circuit.