Channel collector transistor

• US 4,868,624 A
• Filed: 03/14/1986
• Issued: 09/19/1989
• Est. Priority Date: 05/09/1980
• Status: Expired due to Fees

• Current Assignee: Regents of The University of Minnesota (University of Minnesota)
• Original Assignee: Regents of The University of Minnesota (University of Minnesota)
• Inventors: Grung, Bernard L., Zipperian, Thomas E., Warner, Raymond M. Jr.
• Primary Examiner(s): JAMES, ANDREW
• Application Number:
  US06/841,012
• Time in Patent Office: 1,285 Days
• Field of Search: 357/43, 357/13, 357/34, 357/20, 357/59 H
• US Class Current: 257/273
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/7302 structurally associated with other devices assemblies of devices H01L25/00; integrated circuits H01L27/00; IGBT H01L29/7393
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure

Abstract

A monolithic semiconductor transistor structure is described wherein the active collector region of a bipolar-junction transistor is physically and operatively merged with the channel region of a junction field-effect transistor, providing a composite circuit which approximates a cascode configuration. By controlling the integral of the net impurity doping concentration to various active regions of the device, the active collector region of a bipolar-junction transistor configuration is made sufficiently thin so as to simultaneously function as an active collector region as well as a channel region of one or more field-effect transistors. The channel-collector transistor provides high breakdown voltage, high dynamic resistance and linearity over a wide voltage range, and is compatible with solid-state batch fabrication processes for direct incorporation into larger integrated circuits. The device is particularly suitable for linear applications. Improved operating current is obtained and current limiting constraints of the device are minimized by cooperative emitter and base configurations, topologically extended to maximize use of available circuit area. Interdigitated base and collector region layout further improves operating performance.

Claims

1. An improved merged channel-collector transistor semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) a collector region of a second conductivity type opposite to that of said first conductivity type, forming an operative junction with said base region and defining an effective lower collector boundary of said collector region, which underlies and is spaced apart from said base region;

(iii) an emitter region of said second conductivity type forming an operative junction with said base region, said emitter region lying within the lateral extent of said base region;

(iv) that said collector region which is located below substantially the entire said base region and interposed between said base-collector junction and said effective lower collector boundary being sufficiently thin and having controlled impurity concentration therethrough so as to cause said interposed collector region to simultaneously operatively function as an active collector region of a bipolar junction transistor and a channel region of a junction field-effect transistor, wherein the equivalent circuit of said channel-collector sharing field-effect and bipolar junction transistors approximates a cascode configuration;

(v) said emitter being configured such that at least one edge thereof, as viewed in top plan, lies in close proximity with a substantial portion of the periphery of said base region, for minimizing the lateral "L" dimension of that field-effect channel portion of said interposed collector region which comprises the outer peripheral portion thereof but which does not underlie said emitter region; and

(vi) wherein said emitter region is configured with at least one bend in serpentine-shape as viewed in top plan, for increasing the "W" dimension of that field-effect channel portion of said interposed collector region which comprises the outer peripheral portion thereof, but which does not underlie said emitter region; and

(b) means adjacent said effective lower collector boundary of said collector region for preventing majority carrier current flow from said collector region across said lower effective collector boundary.

2. An improved merged channel-collector transistor semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) a collector region of a second conductivity type opposite to that of said first conductivity type, forming an operative junction with said base region and defining an effective lower collector boundary of said collector region, which underlies and is spaced apart from said base region;

(iii) an emitter region of said second conductivity type forming an operative junction with said base region, said emitter region lying within the lateral extent of said base region;

(iv) that said collector region which is located below substantially the entire said base region and interposed between said base-collector junction and said effective lower collector boundary being sufficiently thin and having controlled impurity concentration therethrough so as to cause said interposed collector region to simultaneously operatively function as an active collector region of a bipolar junction transistor and a channel region of a junction field-effect transistor, wherein the equivalent circuit of said channel-collector sharing field-effect and bipolar junction transistors approximates a cascode configuration;

(v) said emitter being configured such that at least one edge thereof, as viewed in top plan, lies in close proximity with a substantial portion of the periphery of said base region, for minimizing the lateral "L" dimension of that field-effect channel portion of said interposed collector region which comprises the outer peripheral portion thereof but which does not underlie said emitter region; and

(vi) wherein said base and said collector regions are configured in interdigitated manner as viewed in top plan; and

(b) means adjacent said effective lower collector boundary of said collector region for preventing majority carrier current flow from said collector region across said lower effective collector boundary.

3. An improved merged channel-collector transistor semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) a collector region of a second conductivity type opposite to that of said first conductivity type, forming an operative junction with said base region and defining an effective lower collector boundary of said collector region, which underlies and is spaced apart from said base region;

(iii) an emitter region of said second conductivity type forming an operative junction with said base region, said emitter region lying within the lateral extent of said base region;

(iv) that said collector region which is located below substantially the entire said base region and interposed between said base-collector junction and said effective lower collector boundary being sufficiently thin and having controlled impurity concentration therethrough so as to cause said interposed collector region to simultaneously operatively function as an active collector region of a bipolar junction transistor and a channel region of a junction field-effect transistor, wherein the equivalent circuit of said channel-collector sharing field-effect and bipolar junction transistors approximates a cascode configuration;

(v) said emitter being configured such that at least one edge thereof, as viewed in top plan, lies in close proximity with a substantial portion of the periphery of said base region, for minimizing the lateral "L" dimension of that field-effect channel portion of said interposed collector region which comprises the outer peripheral portion thereof but which does not underlie said emitter region; and

(vi) wherein as viewed in top plan, said base region is generally U-shaped, and wherein said collector region surrounds the periphery of said base region and has an inwardly directed projection formed in interdigitated manner within the open central portion of said U-shaped base region; and

(b) means adjacent said effective lower collector boundary of said collector region for preventing majority carrier current flow from said collector region across said lower effective collector boundary.

4. An improved merged channel-collector transistor semiconductor device as recited in claim 3, wherein said emitter region is configured with at least one bend in serpentine-like manner in each leg of said U-shaped base region, and extends continuously therebetween.

5. An improved merged channel-collector transistor semiconductor device as recited in claim 4, wherein said base and emitter configurations are symmetrical in top plan about an axis of symmetry.

6. An improved merged channel-collector transistor semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) a collector region of a second conductivity type opposite to that of said first conductivity type, forming an operative junction with said base region and defining an effective lower collector boundary of said collector region, which underlies and is spaced apart from said base region;

(iii) an emitter region of said second conductivity type forming an operative junction with said base region, said emitter region lying within the lateral extent of said base region;

(iv) that said collector region which is located below substantially the entire said base region and interposed between said base-collector junction and said effective lower collector boundary being sufficiently thin and having controlled impurity concentration therethrough so as to cause said interposed collector region to simultaneously operatively function as an active collector region of a bipolar junction transistor and a channel region of a junction field-effect transistor, wherein the equivalent circuit of said channel-collector sharing field-effect and bipolar junction transistors approximates a cascode configuration;

said collector region being further characterized by a zone of relatively increased impurity concentration of said second conductivity-type extending in said interposed collector region between said effective lower collector boundary and said base region and having lateral extent at least that of said base region;

(v) said emitter being configured such that at least one edge thereof, as viewed in top plan, lies in close proximity with a substantial portion of the periphery of said base region, for minimizing the lateral "L" dimension of that field-effect channel portion of said interposed collector region which comprises the outer peripheral portion thereof but which does not underlie said emitter region; and

(b) means adjacent said effective lower collector boundary of said collector region for preventing majority carrier current flow from said collector region across said lower effective collector boundary;

wherein said means adjacent said effective lower collector boundary comprises a layer of said first conductivity-type material, having transverse extent at least that of said base region and forming a p-n junction with said collector region.

7. An improved merged channel-collector transistor semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) a collector region of a second conductivity type opposite to that of said first conductivity type, forming an operative junction with said base region and defining an effective lower collector boundary of said collector region, which underlies and is spaced apart from said base region;

(iii) an emitter region of said second conductivity type forming an operative junction with said base region, said emitter region lying within the lateral extent of said base region;

(iv) that said collector region which is located below substantially the entire said base region and interposed between said base-collector junction and said effective lower collector boundary being sufficiently thin and having controlled impurity concentration therethrough so as to cause said interposed collector region to simultaneously operatively function as an active collector region of a bipolar junction transistor and a channel region of a junction field-effect transistor, wherein the equivalent circuit of said channel-collector sharing field-effect and bipolar junction transistors approximates a cascode configuration; and

(v) said emitter being configured such that at least one edge thereof, as viewed in top plan, lies in close proximity with a substantial portion of the periphery of said base region, for minimizing the lateral "L" dimension of that field-effect channel portion of said interposed collector region which comprises the outer peripheral portion thereof but which does not underlie said emitter region; and

(b) means adjacent said effective lower collector boundary of said collector region for preventing majority carrier current flow from said collector region across said lower effective collector boundary, said means adjacent said effective lower collector boundary comprising a barrier layer of dielectrically isolating material.

8. An improved merged channel-collector transistor semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) a collector region of a second conductivity type opposite to that of said first conductivity type, forming an operative junction with said base region and defining an effective lower collector boundary of said collector region, which underlies and is spaced apart from said base region, said effective lower collector boundary further defining a lower surface of said semiconductor body;

(iii) an emitter region of said second conductivity type forming an operative junction with said base region, said emitter region lying within the lateral extent of said base region;

(iv) that said collector region which is located below substantially the entire said base region and interposed between said base-collector junction and said effective lower collector boundary being sufficiently thin and having controlled impurity concentration therethrough so as to cause said interposed collector region to simultaneously operatively function as an active collector region of a bipolar junction transistor and a channel region of a junction field-effect transistor, wherein the equivalent circuit of said channel-collector sharing field-effect and bipolar junction transistors approximates a cascode configuration;

(v) said emitter being configured such that at least one edge thereof, as viewed in top plan, lies in close proximity with a substantial portion of the periphery of said base region, for minimizing the lateral "L" dimension of that field-effect channel portion of said interposed collector region which comprises the outer peripheral portion thereof but which does not underlie said emitter region; and

(b) means adjacent said effective lower collector boundary of said collector region comprising an air-insulation layer, for preventing majority carrier current flow from said collector region across said lower effective collector boundary; and

(c) means for maintaining said air-insulation layer below said effective collector boundary upon bonding of said semiconductor body to a foreign body.

9. An improved merged channel-collector transistor semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) a collector region of a second conductivity type opposite to that of said first conductivity type, forming an operative junction with said base region and defining an effective lower collector boundary of said collector region, which underlies and is spaced apart from said base region;

(iii) an emitter region of said second conductivity type forming an operative junction with said base region, said emitter region lying within the lateral extent of said base region and formed in a generally U-shaped configuration; and

wherein that portion of said base region which extends in top plan around the outer periphery of said emitter region and between said emitter region and the outer periphery of said base region, has a relatively increased impurity concentration of said first conductivity type and extends relatively deeper into said underlying collector region as compared respectively to like parameters of that portion of said base region which underlies substantially said emitter region;

(iv) that said collector region which is located below substantially the entire said base region and interposed between said base-collector junction and said effective lower collector boundary being sufficiently thin and having controlled impurity concentration therethrough so as to cause said interposed collector region to simultaneously operatively function as an active collector region of a bipolar junction transistor and a channel region of a junction field-effect transistor, wherein the equivalent circuit of said channel-collector sharing field-effect and bipolar junction transistors approximates a cascode configuration; and

(v) said emitter being configured such that at least one edge thereof, as viewed in top plan, lies in close proximity with a substantial portion of the periphery of said base region, for minimizing the lateral "L" dimension of that field-effect channel portion of said interposed collector region which comprises the outer peripheral portion thereof but which does not underlie said emitter region; and

(b) means adjacent said effective lower collector boundary of said collector region for preventing carrier current flow from said collector region across said lower effective boundary.

10. An improved merged channel-collector transistor semiconductor device, comprising:

(a) a collector-providing layer of first conductivity type material having first and second oppositely disposed sides each respectively defining first and second surfaces;

said first side containing a base region of second conductivity type opposite in conductivity to that of said first conductivity type and interdigitated, as viewed in top plan, with said collector layer; and

an emitter region of said first conductivity type within said base region and shaped to conform with the interdigitated shape of said base region, said collector layer and said base and emitter regions each having a portion thereof exposed at said first surface of said device;

said base region being characterized by a first base region underlying at least said emitter region, and a peripheral base region continuous with and skirting or surrounding said first base region and interposed in top plan between said emitter region and said collector region, said peripheral base region being of significantly greater depth as compared with similar parameters of said first base region;

said layer having an active collector region located between said base region and said second surface, wherein that portion of said second surface substantially underlying said base region comprises an effective lower boundary of said active collector region;

(b) means for merging an operative channel portion of a field-effect transistor with at least a portion of said active collector region to form an integrally merged bipolar junction transistor and field-effect transistor device connected in cascode configuration; and

(c) substrate means underlying said second surface of said layer for preventing majority carrier current flow from said collector region across said effective lower boundary portion thereof.

11. An improved merged channel-collector transistor semiconductor device, comprising a body of semiconductor material having first and second surfaces and characterized by:

(a) a collector-providing region of first conductivity-type extending from said second surface;

(b) a base region of second conductivity-type opposite to that of said first conductivity-type, forming an operative p-n junction with said collector region, that portion of said collector region located between said base-collector junction and said second surface and underlying substantially the entire base region, defining an active collector region having a thickness measured between said base-collector junction and said second surface;

(c) an emitter region of said first conductivity-type extending from said first surface and forming an operative p-n junction with said base region, said emitter region being of transverse extent no greater than that of said base region, that portion of said base region located between said emitter-base junction and said collector-base junction and underlying substantially the entire emitter region, defining an active base region having a thickness measured between said emitter-base and said collector-base junctions, the integral of the net impurity concentration of the active base region as taken through said thickness of said active base region being less than 2 10¹² cm⁼² ;

said emitter being configured such that at least one edge thereof, as viewed in top plan lies in close proximity with a substantial portion of the periphery of said base region, for minimizing the later "L" dimension of that portion of said device collector region which comprises the outer peripheral portion thereof but which does not underlie said emitter region;

(d) said active collector region being characterized by a first active collector region substantially underlying said active base region and a second active collector region comprising the remainder of said active collector region, the integral of the net impurity concentration of said first active collector region as taken through said thickness of said active collector region being greater than 10¹¹ cm^-2, and the integral of the net impurity concentration of said second active collector region as taken through said thickness of said active collector region lying in the range of 10¹¹ cm^-2 to 2×

10¹² cm^-2, whereby said active collector region operatively functions simultaneously as a collector of a bipolar junction transistor and a channel of a field-effect transistor, providing a semiconductor device having merged channel-collector transistor properties which approximates a cascode connected equivalent circuit configuration; and

(e) wherein said emitter region is configured with at least one bend in serpentine-shape as viewed in top plan, for increasing the "W" dimension of that field-effect channel portion of said active collector region which comprises the outer peripheral portion thereof, but which does not underlie said emitter region.

12. A semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) an emitter region of a second conductivity type opposite to that of said first conductivity type and forming a junction with said base region, said emitter region having a transverse extent in the direction generally parallel to said upper surface no greater than that of said base region;

(iii) a collector region of said second conductivity type forming a junction with said base region and defining an effective lower collector boundary of said collector region, underlying and spaced from said base region; and

said collector region is further characterized by a zone of relatively increased impurity concentration of said second conductivity-type, extending in said channel-collector region between said effective lower collector boundary and said base region and having lateral extent at least that of said base region;

substantially the entire base region and above said effective lower collector boundary comprising a merged collector region and being sufficiently thin and having impurity concentration controlled therethrough such that said merged collector region operatively functions simultaneously as an active collector region of a bipolar junction transistor and as channel regions of an intervening and an intrinsic junction field-effect transistors;

said channel regions being further characterized by said intervening field-effect transistor channel region comprising at least that portion of said collector region located directly below said emitter region and defined by a control number (N2) of greater than 10¹¹ cm-2, and said intrinsic field-effect transistor channel region comprising the remaining portion of said merged collector region that is located below said base region but outside of said intervening field effect transistor channel region and defined by a control number (N3) lying in the range of about 10¹¹ cm^-2 to 2×

10¹² cm^-2 ;

(b) means adjacent said effective lower collector boundary of said collector region comprising a substrate layer of said first conductivity material, having transverse extent in the direction generally parallel to said upper surface at least that of said base region for preventing majority carrier current flow across said effective lower collector boundary when said device is operatively biased and forming a p-n junction with said collector region; and

(c) means for increasing the current carrying capability of the semiconductor device, comprising means for increasing the current carrying capability of said intervening field-effect transistor channel region, thereby neutralizing its otherwise parasitic current limiting effect on the operation of the semiconductor device.

13. A semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) an emitter region of a second conductivity type opposite to that of said first conductivity type and forming a junction with said base region, said emitter region having a transverse extent in the direction generally parallel to said upper surface no greater than that of said base region;

(iii) a collector region of said second conductivity type forming a junction with said base region and defining an effective lower collector boundary of said collector region, underlying and spaced from said base region;

(iv) that portion of said collector region located below substantially the entire base region and above said effective lower collector boundary comprising a merged collector region and being sufficiently thin and having impurity concentration controlled therethrough such that said merged collector region operatively functions simultaneously as an active collector region of a bipolar junction transistor and as channel regions of an intervening and an intrinsic junction field-effect transistors;

said channel regions being further characterized by said intervening field-effect transistor channel region comprising at least that portion of said collector region located directly below said emitter region and defined by a control number (N2) of greater than 10¹¹ cm-2, and said intrinsic field-effect transistor channel region comprising the remaining portion of said merged collector region that is located below said base region but outside of said intervening field effect transistor channel region and defined by a control number (N3) lying in the range of about 10¹¹ cm^-2 to 2×

10¹² cm^-2 ;

(b) means adjacent said effective lower collector boundary of said collector region and having a transverse extent at least that of said base region for preventing majority carrier current flow across said effective lower collector boundary when said device is operatively biased;

said means adjacent said effective lower collector boundary comprising a barrier layer of dielectrically isolating material; and

(c) means for increasing the current carrying capability of the semiconductor device, comprising means for increasing the current carrying capability of said intervening field-effect transistor channel region thereby neutralizing its otherwise parasitic current limiting effect on the operation of the semiconductor device.

14. A semiconductor device as recited in claim 13, wherein said barrier layer extends to said upper surface and surrounds in moat-like manner said collector, base, and emitter regions.

15. A semiconductor device as recited in claim 13, wherein said dielectrically isolating barrier comprises a layer of silicon dioxide overlying a supportive layer of polycrystalline silicon material.

16. A semiconductor device, comprising:

(a) a body of semiconductor material defining an upper surface and characterized by;

(i) a base region of a first conductivity type extending from said upper surface;

(ii) an emitter region of a second conductivity type opposite to that of said first conductivity type and forming a junction with said base region, said emitter region having a transverse extent in the direction generally parallel to said upper surface no greater than that of said base region;

(iii) a collector region of said second conductivity type forming a junction with said base region and defining an effective lower collector boundary of said collector region, underlying and spaced from said base region;

said effective lower collector boundary further defining a lower surface of said semicondcutor body;

(iv) that portion of said collector region located below substantially the entire base region and above said effective lower collector boundary comprising a merged collector region and being sufficiently thin and having impurity concentration controlled therethrough such that said merged collector region operatively functions simultaneously as an active collector region of a bipolar junction transistor and as channel regions of an intervening and an intrinsic junction field-effect transistors;

said channel regions being further characterized by said intervening field-effect transistor channel region comprising at least that portion of said collector region located directly below said emitter region and defined by a control number (N2) of greater than 10¹¹ cm-2, and said intrinsic field-effect transistor channel region comprising the remaining portion of said merged collector region that is located below said base region but outside of said intervening field effect transistor channel region and defined by a control number (N3) lying in the range of about 10¹¹ cm^-2 to 2×

10¹² cm^-2 ;

(b) means adjacent said effective lower collector boundary of said collector region comprising an air-insulation layer and having a transverse extent at least that of said base region for preventing majority carrier current flow across said effective lower collector boundary when said device is operatively biased;

(c) means for increasing the current carrying capability of the semiconductor device, comprising means for increasing the current carrying capability of said intervening field-effect transistor channel region thereby neutralizing its otherwise parasitic current limiting effect on the operation of the semiconductor device; and

(d) means for maintaining said air-insulation layer below said effective lower collector boundary upon bonding of said semiconductor body to a foreign body.