Insulated-gate semicustom integrated circuit

• US 4,868,705 A
• Filed: 02/18/1988
• Issued: 09/19/1989
• Est. Priority Date: 02/23/1987
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shiochi, Masazumi, Ugawa, Akimitsu
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Osborn, David
• Application Number:
  US07/156,740
• Time in Patent Office: 579 Days
• Field of Search: 361/56, 361/90, 361/91, 361/111, 361/110, 357/22 C,22 D,22 F,22 G, 357/23.1, 357/23.13, 357/41, 307/304, 307/303
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

Incorporated in a MOS semicustom integrated circuit are pull-up and pull-down MOS transistors adapted for pulling up or down the potential of a signal line connecting a protection circuit with an internal circuit to be protected from electrostatic breakdown. The MOS transistors have their drains connected together to the signal line and their sources connected to a pull-up power supply node or pull-down power supply node as required. The MOS transistor acts as a pull-up or pull-down transistor when its source is connected to the pull-up or pull-down supply node by master slice wiring, and its drain junction acts as a protective diode when its source remains open. Thus, owing to the protection functions of the drain junction and diodes in the protection circuit, the electrostatic breakdown strength of the internal circuit can be increased without increase in the occupied area of the protection circuit in the integrated circuit.

Claims

1. An insulated-gate semicustom integrated circuit comprising:

a protection circuit comprising

first protective diodes each having one end connected to a first signal line, and

a resistor element inserted in said first signal line, said first signal line having one end connected to one end of a first input pad and a first output pad; and

a second protective diode comprising a pull-up/down MOS transistor having a drain connected to a second signal line, a source remaining open, and a gate connected to a fixed potential, said second signal line connecting a second end of said first signal line to a first internal circuit.

2. An insulated-gate semicustom integrated circuit according to claim 1, wherein said MOS transistor functions as a pull-up transistor when its source is connected to a power supply node by a master slice wiring method.

3. An insulated-gate semicustom integrated circuit according to claim 2, further comprising a further MOS transistor connected between said drain of said MOS transistor and said second signal line.

4. An insulated-gate semicustom integrated circuit according to claim 3, wherein said further MOS transistor has a source connected to the drain of said MOS transistor.

5. An insulated-gate semicustom integrated circuit according to claim 3, wherein said further MOS transistor has a source connected to a power supply.

6. An insulated-gate semicustom integrated circuit according to claim 1, wherein said MOS transistor functions as a pull-down transistor when its source is connected to a power supply node by a master slice wiring method.

7. An insulated-gate semicustom integrated circuit according to claim 6, further comprising a further MOS transistor connected between said drain of said pull-up/down MOS transistor and said second signal line.

8. An insulated-gate semicustom integrated circuit according to claim 7, wherein said further MOS transistor has a source connected to the drain of said pull-up/down MOS transistor.

9. An insulated-gate semicustom integrated circuit according to claim 7, wherein said further MOS transistor has a source connected to a power supply.

10. An insulated-gate semicustom integrated circuit according to claim 1, further comprising:

an additional protection circuit comprising

additional first protective diodes each having one end connected to an additional first signal line, and

an additional resistor element inserted in said additional first signal line, said additional first signal line having one end connected to one end of an additional input pad and an additional output pad; and

an additional second protective diode comprising an additional pull-up/down MOS transistor having a drain connected to an additional second signal line, a source remaining open, and a gate connected to a power source potential, said additional second signal line connecting a second end of said additional first signal line to an additional first internal circuit.