Operating system independent virtual memory computer system

• US 4,868,738 A
• Filed: 08/15/1985
• Issued: 09/19/1989
• Est. Priority Date: 08/15/1985
• Status: Expired due to Fees

• Current Assignee: Lanier Worldwide Incorporated (Ricoh Company Limited)
• Original Assignee: Lanier Worldwide Incorporated (Ricoh Company Limited)
• Inventors: Burleson, David B., Alcorn, John S., Kish, John W.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Munteanu, Florin
• Application Number:
  US06/766,024
• Time in Patent Office: 1,496 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/26
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

An improved virtual memory computer system comprising a main processing unit for executing application and operating system software without virtual memory code and independently of virtual memory operation. A dedicated second processing unit is provided for maintaining a memory map, which translates addresses in the main processing unit address space into physical memory addressess of a primary memory. A network interface allows pages or segments of data from a secondary memory connected to a communications network to be transferred into the primary memory in a manner transparent to the operation of the main processing unit. A direct memory access (DMA) circuit transfer the header portion of a network-transferred page of data into a separate auxiliary addressable memory for storage of network overhead information, while the useful data portions of the page are stored directly in locations in the primary addressable memory. A requested page of data is then placed directly in a desired location in primary memory without the need for moving or retransferring the data within the primary memory to strip off network header information after a DMA transfer. The system is responsive to detect and correct a page fault condition prior to execution of the main processing unit instruction which generated the page fault, which obviates reexecution of instructions or correction of instruction execution results by the main processing unit.

Claims

1. An improved main processing unit operating system independent virtual memory computer system, comprising:

memory means having an 2ⁿ word actual address space for storage of instructions and data for producing by said computer system;

a main processing unit operative to provided a fetching address within an 2^m word virtual address space, where m is greater than n, for fetching instructions or data from said memory means and to execute a set of first instructions for processing data in said computer system and for running operating system software; and

a secondary processing unit responsive to said fetching address provided by said main processing unit for executing virtual memory management software, said virtual memory management software comprising a set of second instruction executable independently of said set of first instructions and operative for providing instructions or data to said memory means for accessing by said main processing unit from an actual address in said memory means corresponding to said fetching address, said set of second instructions being executable only on said secondary processing unit,

said main processing unit being operative to process data and execute user application or operating system instructions within said virtual address space without executing any of said first instructions for implementing or maintaining virtual memory and said secondary processing unit being incapable of executing any of said first instructions.

2. The improved virtual memory computer system of claim 1, further comprising memory map means for translating said fetching address to an address in said actual address space.

3. The improved virtual memory computer system of claim 1, wherein said memory means is a primary addressable memory, and further comprising:

a secondary addressable memory; and

wherein said secondary processing unit retrieves instructions or data from said secondary addressable memory and stores said retrieved instructions or data in said primary addressable memory at an actual address in said actual address space corresponding to said fetching address.

4. The improved virtual memory system of claim 1, wherein said memory means is a primary memory means, and further comprising:

page fault detecting means responsive to said fetching address provided by said main processing unit for detecting the occurrence of a page fault condition, said page fault condition occurring if said fetching address corresponds to data requested by said main processing unit not currently resident in said primary memory means, and

wherein said secondary processing unit is responsive to the detection of said page fault condition by said page fault detecting means for retrieving said requested data from a second memory means corresponding to said fetching address and for storing said requested data in said primary memory for accessing by said main processing unit.

5. The improved virtual memory computer system of claim 4, wherein said primary means is operative to provide said data or instructions to said main processing unit in response to said fetching address,

wherein in response to a page fault condition said secondary processing unit retrieves said requested data or instructions from said second memory and stores said requested data or instructions in said primary memory means responding to said fetching address

whereafter said primary memory means provides said requested data or instructions to said main processing unit in response to said fetching address.

6. The improved virtual memory computer system of claim 4, wherein said main processing unit has a plurality of operating cycles including an address cycle wherein said fetching address is provided to said primary memory and an instruction cycle for executing a previously-fetched instruction,

wherein said secondary processing unit suspends said address cycle in response to said page fault condition, and

wherein said secondary processing unit retrieves said requested data or instructions from said second memory means and stores said requested data or instructions in said primary memory means, and then allows completion of said address cycle.

7. The improved virtual memory computer system of claim 6, further comprising means responsive to the detection of said page fault condition for temporarily halting the execution of operating cycles of said main processing unit until correction of said page fault condition.

8. An improved main processing unit operating system independent virtual memory computer system, comprising:

memory means having an n word actual address space for storage of instructions and data for processing by said computer system;

a main processing unit operative to provide a fetching address within an m word virtual address space, where m is greater than n, for fetching instructions or data from said memory means and to execute a set of first instructions for processing data in said computer system and for running operating system software without virtual memory capability; and

virtual memory management means operative independently of said main processing unit and said operating system software in response to said fetching address provided by said main processing unit for temporarily halting operation of said main processing unit, for providing instructions or data to said memory means for accessing by said main processing unit from an actual address in said memory means corresponding to said fetching address, and for subsequently allowing said main processing unit to continue operation,

said main processing unit being operative to process data and execute instructions within said virtual address space independently of the operation of said virtual memory management means without execution of any programs or overhead processing by said main processing unit for virtual memory.

9. An improved virtual memory computer system, comprising:

a primary addressable memory having a p-bit primary memory address space corresponding to a predetermined first number 2p of physical addressable locations, where p is an integer;

a secondary addressable memory;

a third addressable memory;

a main processing unit having n address lines, where n is an integer, and capable of addressing a first processor address space corresponding to 2ⁿ words of memory;

means defining a second address space having m address lines, where m is an integer, and capable of addressing 2^m words of memory, said second address space comprising a first portion and a second portion;

memory map means for translating input addresses in said first processor address space and said second portion of said second address space to addresses in said primary memory address space; and

means for retrieving a page of digital data from said secondary addressable memory and for storing said retrieved page at addresses corresponding to said second addresses corresponding to said second address space,

said page retrieving means being responsive to generate addresses in said second address space such that a first page portion of said retrieved page is stored in said third addressable memory at addressable locations corresponding to said first portion of said second address space and a second page portion of said retrieved page is stored in said primary addressable memory at addressable locations corresponding to said second portion of said second address space for accessing by said main processing unit.

10. The improved virtual memory computer system of claim 9

wherein said third addressable memory has a third memory address space, and

wherein said first portion of said second address space corresponds to a plurality of addressable locations in said third addressable memory and said second portion of said second address space corresponds to a plurality of locations in said primary addressable memory,

whereby said first page portion of a retrieved page is stored in said third addressable memory.

11. The improved virtual memory computer system of claim 9, wherein said first page portion of said retrieved page comprises a header portion and said second page portion of said retrieved page comprises instructions or data for said main processing unit.

12. The improved virtual memory computer system of claim 9, wherein said page retrieving means comprises direct memory access (DMA) means responsive to automatically generate said addresses in said second address space when a page of digital data is retrieved by said page retrieving means.

13. The improved virtual memory computer system of claim 9, wherein m is greater than p.

14. The improved virtual memory computer system of claim 9, wherein said means defining a second address space comprises direct memory access (DMA) means responsive to automatically generate said addresses in said second address space for said page retrieving means when a page of digital data is retrieved by said page retrieving means.

15. The improved virtual memory computer system of claim 9, wherein said means defining a second address spaced comprises a second processing unit having m address lines.

16. The improved virtual memory computer system of claim 15, further comprising memory management means responsive to input addresses in said first processor address space and said second portion of said second address space provided to said memory map means for coordinating access to said primary addressable memory between said main processing unit and said second processing unit.

17. The improved virtual memory computer system of claim 15, wherein said second processing unit is operative to modify entries in said memory map means so that said memory map means correctly translates said input addresses to addresses in said primary addressable memory when a page is retrieved by said page retrieving means.

18. The improved virtual memory computer system of claim 15, wherein said memory map means is responsive to translate addresses in predetermined portions of said second address space to addresses in said primary addressable memory.

19. The improved virtual memory computer system of claim 15, wherein said page retrieving means retrieves said page of digital data from said secondary addressable memory in response to signals from said second processing unit.

20. The improved virtual memory computer system of claim 9, wherein said memory map means comprises an addressable memory comprising a plurality of addressable locations for storing a plurality of map entries, each of said map entries comprising an address in said primary memory corresponding to an input address in said first processor address space or an input address in said second portion of said second address space.

21. The improved virtual memory computer system of claim 9, wherein said secondary addressable memory comprises a disk drive.

22. The improved virtual memory computer system of claim 9, further comprising communication means for transmitting said retrieved page of digital data from said secondary addressable memory to said primary addressable memory.

23. The improved virtual memory computer system of claim 22, wherein said communication means comprises a digital serial network communications controller operative to transmit and receive digital data over a serial data link;

and

network control means operative to transfer said retrieved page from said secondary addressable memory through said serial data link into said primary addressable memory upon command by said page retrieving means.

24. The improved virtual memory computer system of claim 9, wherein said first processor address space is a first first processor address space, and further comprising means defining for said main processing unit a second n-bit first processor address space corresponding to 2ⁿ additional words of memory.

25. The improved virtual memory computer system of claim 9 further comprising means for relating a predetermined set of addresses in said second address space corresponding to a predetermined portion of said first processor address space to addresses in said primary addressable memory such that at least a predetermined portion of addresses in said second address space correspond to addresses in said primary addressable memory.

26. An improved virtual memory computer system, comprising:

a primary addressable memory having a primary memory address space corresponding to a predetermined first number 2^p of physical addressable locations, where p is an integer;

a secondary addressable memory having a predetermined second number of physical addressable locations;

a main processing unit having an n-bit address field, where n is an integer, and capable of addressing a first processor address space corresponding to 2ⁿ words of memory;

a third addressable memory having a third memory address space corresponding to a predetermined third number of physical addressable locations;

a second processing unit capable of addressing a second processor address space, said second processor address space comprising a first portion corresponding to addressable locations in said third addressable memory and a a second portion corresponding to addressable locations in another addressable memory;

memory map means for translating addresses in said first processor address space and said second portion of said second processor address space to addresses in said primary memory address space; and

direct memory access (DMA) means for retrieving a page of digital data from said secondary addressable memory and for storing a retrieved page at addresable locations in said second processor address space, said retrieved page comprising a header portion and a data portion,

said DMA means being operative to generate addresses in said second processor address space upon the retrieval of said retrieved page from said secondary addressable memory such that said header portion of said retrieved page is stored at addressable locations corresponding to said first portion of said second processor address space and said data portion of said retrieved page is stored at addressable locations corresponding to said second portion of said second processor address space,

whereby said header portion is stored in said third addressable memory and said data portion is stored in said primary addressable memory for accessing by said main processing unit through said memory map means.

27. The improved virtual memory computer system of claim 26, further comprising memory management means responsive to input addresses in said first processor address space and said second portion of said second processor address space provided to said memory map means for coordinating access to said primary addressable memory between said main processing unit and said second processing unit.

28. The improved virtual memory computer system of claim 26, where p is less than n.

29. The improved virtual memory compute system of claim 26, further comprising means for relating a predetermined set of addresses in said second processor address space corresponding to a predetermined portion of said first processor address space to addresses in said primary addressable memory, such that at least a predetermined portion of addresses in said second processor address space correspond to addresses in said primary addressable memory.

30. The improved virtual memory computer system of claim 26, wherein said memory map means comprises an addressable memory comprising a plurality of addressable locations for storing a plurality of map entries, each of said map entries comprising an address in said primary addressable memory corresponding to an input address in said first processor address space or an input address in said second portion of said second processor address space.

31. The improved virtual memory computer system of claim 30, wherein said second processing unit is operative to maintain said memory map by modifying said map entries so that said map entries relate to an addressable location in said primary addressable memory at which data corresponding to addresses in said first processor address space and addresses in said second portion of said second processor address space is stored.

32. An improved main processing unit operating system independent virtual memory computer system, comprising:

a main processing unit having a plurality of operating cycles including an address cycle wherein an address of a primary addressable memory containing data to be retrieved by said main processing unit is provided on an address bus as an output address and data provided to said main processing unit over a data bus in response thereto from said primary addressable memory, and an instruction cycle wherein said main processing unit executes a previously retrieved instruction; and

virtual memory means operative independently of operating system software for said main processing unit, comprising;

page fault detecting means responsive to an output address provided on said address bus for detecting the occurrence of a page fault condition, said page fault condition occurring if an output address for a particular address cycle corresponds to data not currently resident in said primary addressable memory;

page fault correcting means responsive to the occurrence of said page fault condition for suspending said particular address cycle, for retrieving data corresponding to said output address from a secondary addressable memory, for storing retrieved data corresponding to said output address in said primary addressable memory, and for thereafter allowing said main processing unit to compete said particular address cycle and begin a subsequent operating cycle.

33. The improved virtual memory computer system of claim 32, wherein said virtual memory means is responsive to the absence of a page fault condition for providing data on said data bus from an addressable location in said primary addressable memory corresponding to said output address.

34. The improved virtual memory computer system of claim 32, wherein said page fault detecting means comprises memory map means including an addressable memory having a plurality of addressable locations for storing a plurality of map entries, each of said map entries containing data indicative of whether said output address from said main processing unit corresponds to data present in said primary addressable memory.

35. The improved virtual memory computer system of claim 32, wherein said page fault correcting means comprises a second processing unit operating independently of said main processing unit.

36. A computer system, comprising:

a first processing unit having n address lines, wherein n is an integer, and capable of addressing a first processor address space corresponding to 2ⁿ words of memory;

a second processing unit having m address lines, where m is an integer and capable of addressing a second processor address space corresponding to 2^m words of memory;

a primary addressable memory having p address lines, where p is an integer, and defining a primary memory address space corresponding to a predetermined number 2^p of physical locations for storing data, said primary addressable memory being accessible by said first and said second processing units; and

memory map means for translating addresses in said first processor address space and said second processor address space to addresses in said primary memory address space by providing a plurality of map entries, each of said map entries relating an address in said first or said second processor address space to an address in said primary memory address space, said first processor address space including a predetermined portion which does not correspond to addresses in said primary memory address space,

said memory map including a plurality of map entries which relate a predetermined set of addresses in said second processor address space corresponding to said predetermined portion of said first processor address space to addresses in said primary addressable memory,

so that map entries corresponding to said predetermined portion of said first processor address space are made available for use by said second processing unit.

37. The computer system of claim 36, wherein said predetermined portion of said first processor address space is not used by said first processing unit so that map entries which would otherwise be available for use by said first processing unit are used by said second processing unit are used by said second processing unit.

38. The computer system of claim 36, wherein said first and said second processing units access said primary memory over a common data transfer means, and further comprising processor arbiter means responsive to a request from one of said first or said second processing units for seizing said data transfer means for a data transfer to or from said primary addressable memory.

39. The computer system of claim 36, wherein said predetermined portion of said first processor address space corresponds to addresses in an auxiliary addressable memory accessable only by said first processing unit.

40. A virtual memory multi-processor computer system, comprising:

a primary addresable memory having p address lines corresponding to a primary memory address space corresponding to a predetermined first number 2p of physical addressable locations, where p is an integer, and having a primary memory data bus;

a first processing unit having n address lines and capable of addressing a first processor address space corresponding to 2ⁿ words of memory, where n is an integer,

said first processing unit having a plurality of operating cycles including an address cycle wherein an address of said primary addressable memory to be accessed for a memory operation is provided on a first address bus as an output address together with a memory request signal, and data provided from or to said first processing unit over a first data bus in response thereto from or to said primary addressable memory, and an instruction cycle wherein said first processing unit executes a previously-retrieved instruction;

a second processing unit having m address lines, where m is an integer, and capable of addressing a second processor address space corresponding to 2^m words of memory,

said second processing unit having a plurality of operating cycles including an address cycle wherein an address of said primary addressable memory to be accessed memory to be accessed for a memory operation is provided on a second address bus as an output address together with a memory request signal, and data provided from or to said second processing unit over a second data bus in response thereto from or to said primary addressable memory, and an instruction cycle wherein said second processing unit executes a previously-retrieved instruction;

arbiter means responsive to said memory request signal from a requesting processing unit, said requesting processing unit comprising the particular one of said first or said second processing units first providing said memory request signal, for enabling said requesting processing unit to access said primary addressable memory for said memory operation and for temporarily disabling the nonrequesting one of said first or said second processing units from completing its respective said address cycle until said requesting processing unit has completed said memory operation;

address validity detecting means for detecting when an address provided to said primary addressable memory from at least one of said processing units corresponds to data currently resident in said primary addressable memory and for providing a page valid signal in response thereto;

trap means responsive to the absence of said page valid signal for temporarily halting said at least one of said processing units from completing its said address cycle and for providing a trap signal to the other one of said processing units, said other processing unit being responsive to said trap signal to retrieve data from a secondary addressable memory corresponding to said address from said at least one of said processing units and to place said data in said primary addressable memory; and

address and data multiplexing means for multiplexing said first and said second address buses to said primary addressable memory address lines, and said first and said second data buses to said primary addressable memory data bus.

41. The multi-processor computer system of claim 40, further comprising address translation means connected to the output of said address multiplying means for translating addresses on said first and said second address buses into addresses of said primary addressable memory.

42. The multi-processor computer system of claim 40, wherein p is less than n or m, and said address translation means comprises virtual memory means.

43. An improved main processing unit operating system independent virtual memory computer system, comprising:

primary memory means having an 2ⁿ word actual address space for storage of instructions and data for processing by said computer system;

a main processing unit operative to provide a fetching address within an 2^m word virtual address space, where m is greater than n, for fetching instructions or data from said memory means and to execute a set of first instructions for processing data in said computer system and for running operating system software, said main processing unit being operative to process data and execute user application or operating system instructions within said virtual address space without executing any of said first instructions for implementing or maintaining virtual memory;

a secondary processing unit responsive to said fetching address provided by said main processing unit for executing a set of second instructions independently of said set of first instructions for providing instructions or data to said memory means for accessing by said main processing unit from an actual address in said memory means corresponding to said fetching address;

page fault detecting means responsive to said fetching address provided by said main processing unit for detecting the occurrence of a page fault condition, said page fault condition occurring if said fetching address corresponds to data requested by said main processing unit not currently resident in said primary memory means;

said secondary processing unit being responsive to the detection of said page fault condition by said page fault detecting means for retrieving said requested data from a second memory means corresponding to said fetching address and for storing said requested data in said primary memory means for accessing by said main processing unit;

said primary memory means being operative to provide said data or instructions to said main processing unit in response to said fetching address;

said secondary processing unit being operative in response to a page fault condition to retrieve said requested data or instructions from said second memory means and store said requested data or instructions in said primary memory means prior to said primary memory means responding to said fetching address,

whereafter said primary memory means provides said requested data or instructions to said main processing unit in response to said fetching address.

44. An improved main processing unit operating system independent virtual memory computer system, comprising:

primary memory means having an 2ⁿ word actual address space for storage of instructions and data for processing by said computer system;

a main processing unit operative to provide a fetching address within an 2^m word virtual address space, where m is grater than n, for fetching instructions or data from said memory means and to execute a set of first instructions for processing data in said computer system and for running operating system software,

said main processing unit being operative to process data and execute user application or operating system instructions within said virtual address space without executing any of said first instructions for implementing or maintaining virtual memory,

said main processing unit having a plurality of operating cycles including an address cycle wherein said fetching address is provided to said primary memory and an instruction cycle for executing a previously-fetched instruction;

page fault detecting means responsive to said fetching address provided by said main processing unit for detecting the occurrence of a page fault condition, said page fault condition occurring if said fetching address corresponds to data requested by said main processing unit not currently resident in said primary memory means; and

a secondary processing unit responsive to said fetching address provided by said main processing unit for executing a set of second instructions independently of said set of first instructions for providing instructions or data to said memory means for accessing by said main processing unit from an actual address in said memory means corresponding to said fetching address,

said secondary processing unit being responsive to the detection of said page fault condition by said page fault detecting means for retrieving requested data from a second memory means corresponding to said fetching address and for storing said requested data in said primary memory means for accessing by said main processing unit,

said secondary processing unit being operative to suspend said address cycle in response to said page fault condition, and to retrieve said requested data or instructions from said second memory means and store said requested data or instructions in said primary memory means, and then allow completion of said address cycle.