Computer bus deadlock prevention

• US 4,868,741 A
• Filed: 11/25/1986
• Issued: 09/19/1989
• Est. Priority Date: 07/22/1983
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Schneider, Daniel E., Gula, James L.
• Primary Examiner(s): MOORE, MARGARET G
• Assistant Examiner(s): MOORE, MARGARET G
• Application Number:
  US07/934,584
• Time in Patent Office: 1,029 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/113
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4036 and deadlock prevention

Abstract

A digital computing system includes at least a first and a second bus with at least a first master connected to the first bus and a second master connected to the second bus. The first master is capable of requesting the second bus through the first bus and the second master is capable of requesting the first bus through the second bus. Central conversion means receives both requests and has circuitry for generating a response signal to the first bus when both requests come simultaneously. The first master receives the response signal and continues the cycle, but without continuing the request for the second bus. The cycle is completed as though the request had been completed.

Claims

1. A digital computing system including at least a first and a second bus, with at least a first master connected to the first bus and a second master conected to the second bus, the first master connected to initiate a cycle requesting the second bus through the first bus and the second master connected to initiate a cycle requesting the first bus through the second bus, the system comprising:

(a) central conversion means coupled to said first and second buses for receiving the bus requests from the first and second masters through the first and second buses, respectively, for the second and first buses, respectively, the central conversion means including means for generating a response signal to the first bus indicative that the first bus and the second bus are requested simultaneously by the second and first masters respectively, and means for receiving and means for decoding the response signal; and

(b) means connected to receive the decoded signal and responsive thereto for causing the first master to disconnect its request for the second bus, and including means for causing the first master to proceed to the end of its request cycle to be in a condition to again arbitrate for the second bus, thereby avoiding a deadlock between the simultaneous requests.

2. The system of claim 1 wherein the means for generating a response signal comprises a programmable array of logic for receiving signals generated from the first and second master indicative of the simultaneous bus request and for generating signals in response thereto for decoding by the means for receiving and decoding.

3. The system of claim 2 wherin the means for receiving and decoding the response signals comprise register means for receiving the response signals and providing output signals indicative of the simultaneous request condition.

4. The system of claim 3 wherein the means for causing the first master to disconnect its request for the second bus comprises means for continuing the cycle requesting the second bus without continuing the request for the second bus until the cycle is normally terminated.