Shared lines equipment, especially for B-ISDN switching system

• US 4,868,812 A
• Filed: 05/11/1988
• Issued: 09/19/1989
• Est. Priority Date: 05/13/1987
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Kruger, Johann E. W., Killat, Ulrich R. P., Jasmer, Wolfgang E.
• Primary Examiner(s): Orsino, Joseph A.
• Assistant Examiner(s): Scutch, III, Frank M.
• Application Number:
  US07/192,814
• Time in Patent Office: 496 Days
• Field of Search: 370/58, 370/56, 370/85, 370/110.1, 340/825.5, 379/333, 379/334
• US Class Current: 370/369
• CPC Class Codes: H04J 2203/0003 Switching fabrics, e.g. transport network, control network
• CPC Class Codes: H04J 2203/0039 Topology
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

Large-scale time-division switching arrangements often consist of a central switching network and a series of so-called concentrators. For establishing an H1 switching a series of wideband concentrators are connected to a central wideband switching network if the wideband concentrators are of a modular structure and communicate through an internal bus system and an interface circuit with the central wideband switching network connected thereto, a distribution switching in the direction of the subscriber station and a testing of the concentrators while in operation can be effected in a simple way.

Claims

1. Apparatus for shared lines for a B-ISDN switching system having subscriber stations, wideband concentrators and a central wideband switching network, the apparatus comprising:

wideband concentrators (K) of a modular structure, which each include;

(a) an internal bus system (RB) and

(b) an interface circuit (H2i) for coupling with the central wideband switching network (Z), so that the wideband concentrators communicate with the central wideband switching network via the internal bus system and the interface circuit.

2. The apparatus of claim 1, wherein

(a) the wideband concentrators each comprise at least one concentrator module (C) which includes:

(i) two memory banks (A,B);

(ii) a serial to parallel converter (S/P);

(iii) a parallel-to-serial converter (P/S), the two memory banks communicating with the internal bus system via the serial-to-parallel and parallel-to-serial converter,

(iv) an H1 interface circuit (H1SS) for communicating between the two memory banks and a subscriber group circuit (TG),

so that during each frame period data are written to only one of the two memory banks and data are only read out from the other of the two memory banks.

3. Apparatus for shared lines for a B-ISDN switching system which includes subscriber stations and a central wideband switching network, the apparatus comprising a least one wideband concentrator (K) for coupling between the subscriber stations and the central wideband switching network, each wideband concentrator comprising:

(a) at least one internal bus system (RB);

(b) at least one interface circuit (H2i) for coupling with the central wideband switching network (Z); and

(c) at least one concentrator module (C) which includes;

(i) two memory banks (A,B);

(ii) a serial-to-parallel converter (S/P);

(iii) a parallel-to-serial converter (P/S), the two memory banks communicating with the internal bus system via the serial-to-parallel and parallel-to-serial converters; and

(iv) an H1 interface circuit (H1SS) for communicating between the two memory banks and a subscriber group circuit (TG);

so that during each frame period data are written to only one of the two memory banks and data are only read out from the other of the two memory banks and so that the wideband concentrator communicates via the internal bus system and the interface circuit to the central wideband switching network.

4. The apparatus of claim 3 wherein each of the two memory banks is a double memory bank.

5. The apparatus of claim 3 wherein:

(a) each such concentrator module further comprises a control circuit (ST); and

(b) the one of the two memory banks has two modes;

(i) a first, counter-addressed mode for receiving data to be written to the one of the two memory banks from the bus system; and

(ii) a second, addressed mode in which the control circuit reads out data from the one of the two memory banks using a clock signal reduced by an integral factor.

6. The apparatus of claim 3 wherein each such concentrator module (C) includes a bus access circuit (B-SE) for controlling access of the concentrator module to the internal bus system.

7. The apparatus of claim 3 wherein each such concentrator module (C) which includes

(a) a switch (S) coupled with the two memory banks;

and

(b a loop circuit (S-OE) for controlling the switch.

8. The apparatus of claim 3 comprising n interface circuits (H2i) and n internal bus systems (RB), so that the apparatus is arranged according to the (n,k) concept, where k and n are integers.

9. The apparatus of claim 7, further comprising an elastic store (ES) connected to the H1 interface circuit (H1SS) and the switch (S).

10. The apparatus of claim 9 wherein each such concentrator module transmits a free signal through the H1 interface in the direction of a subscriber group circuit if a time channel is not occupied.

11. The apparatus of claim 7, wherein each such concentrator module further comprises a delay element (V) coupled between the two memory banks.

12. The apparatus of claim 11 wherein the delay element comprises a plurality of D flipflops.

13. The apparatus of claim 8 further comprising a plurality of concentrator time stages, one for each internal bus system.

14. The apparatus of claim 13, further comprising at least one clock synchronization circuit (TS) each connected to a respective one of the internal bus systems (RB), each clock synchronization circuit comprising:

(a) a free-running start-stop oscillating (O) and

(b gate and trigger circuits connected to the oscillator.

15. The apparatus of claim 14, wherein

the clock synchronization circuit further comprises four flipflops (FF) connected to the respective one of the internal bus systems;

and

the oscillator (O) has an adjustable delay line and the oscillator (O) is triggered by one of the four flipflops.

16. The apparatus of claim 15, further comprising a shift register (SR) coupled to receive a bit sequence "1011" and connected to the oscillator (O) and a set input of the flipflops. (FF).