Microcomputer capable of accessing internal memory at a desired variable access time

• US 4,870,562 A
• Filed: 03/20/1987
• Issued: 09/26/1989
• Est. Priority Date: 03/20/1986
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Nishiguchi, Yukihiro, Kimoto, Manabu
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US07/028,513
• Time in Patent Office: 921 Days
• Field of Search: 364/200, 364/900, 364/569
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A microcomputer includes an instruction execution unit and an internal memory formed on the same chip. A first circuit is provided for setting a memory access cycle for a read/write to the internal memory shorter than that for read/write to an external memory. Further, a second circuit is provided for setting the memory access cycle for the read/write to the internal memory substantially equal to that for the read/write to the external memory. The first and second setting circuits are alternatively and selectively activated.

Claims

1. A microcomputer which includes an instruction execution unit and an internal memory formed on the same chip, comprising a first means for setting a memory access cycle for a read/write to the internal memory shorter than that for read/write to an external memory, a second means for setting the memory access cycle for the read/write to the internal memory substantially equal to that for the read/write to the external memory, and means for selectively activating one of the first and second setting means.

2. A microcomputer as claimed in claim 1 wherein the first means includes a first circuit generating a first memory access timing signal having a length shorter than the memory access cycle for the external memory, and the second means includes a second circuit generating a second memory access timing signal having a length substantially equal to the memory access cycle for the external memory.

3. A microcomputer as claimed in claim 2 further including an address discriminator adapted to discriminate whether an address to be accessed designates the internal memory or the external memory, the discriminator operating to activate the first means when the address to be accessed designates the internal memory and to activate the second means when the address to be accessed designates the external memory.

4. A microcomputer as claimed in claim 3 further including a third means responsive to a mode setting signal to cause the selective activating means to activate the second means irrespectively of whether the address to be accessed designates the internal memory.

5. A microcomputer as claimed in claim 3 wherein the address discriminator includes an OR circuit receiving at least the most significant bit of a address information on an internal address bus in the microcomputer.

6. A microcomputer as claimed in claim 5 wherein the OR circuit also receives the mode setting signal.

7. A microcomputer as claimed in claim 1 further including a third means responsive to a mode setting signal to cause the selective activating means to activate the second means irrespectively of whether the address to be accessed designates the internal memory.

8. A microcomputer as claimed in claim 1 further including a timing controller, comprising said first means and said second means, said controller being operative to receive an address output timing signal for generating a data read/write timing signal, to terminate the read/write timing signal at only one clock cycle when the address to be accessed designates the internal memory, and to expand the read/write timing signal to a length of a plurality of clock cycles when the address to be accessed designates the external memory.

9. A microcomputer as claimed in claim 8 wherein the timing controller has a pair of feedback paths for returning the read/write timing signal to an initial condition when the read/write timing signal has changed, one of the feedback paths having a delay time shorter than that of the other feedback path, the one feedback path being activated when the address to be accessed designates the internal memory, and the other feedback path being activated when the address to be accessed designates the external memory.

10. A microcomputer as claimed in claim 9 wherein the other feedback path is activated and the one feedback path is cut off when it is required to make the access time of the internal memory consistent with that of the external memory.

11. A microcomputer as claimed in claim 1 wherein the instruction execution unit includes a CPU, and further including a timing controller receiving at least an address discrimination signal indicative of whether or not an address to be accessed indicates the external memory, an instruction fetch control signal, and a pair of clock signals, the timing controller generating at least an external memory fetch signal and a pair of CPU clock signals to the CPU, the timing controller being controlled to maintain the CPU clocks at fixed condition for a predetermined time length independently of the clock signals when an address to be accessed designates the external memory.