Scannerless message concentrator and communications multiplexer

• US 4,870,566 A
• Filed: 08/27/1984
• Issued: 09/26/1989
• Est. Priority Date: 08/27/1984
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pescatore, John C., Matlack, Richard C. Jr., Smith, Robert L. Jr., Cooper, Ronald J., Marsico, Mario A.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/644,889
• Time in Patent Office: 1,856 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/113
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A communications concentrator and message multiplexer featuring direct access from the communications adapters to main memory via direct memory access means which eliminates the usual scanner or polling facility in a concentrator or multiplexer is described. A control microprocessor manages the allocation of memory, the conversion of message protocols and the servicing of interrupts to a plurality of port interface adapter microprocessors. The interface adapter microprocessors directly set up and control the DMA operation instead of having the DMA operation controlled by the control processor. One of the port adapters serves as a service adapter over a dedicated interface allowing a remote disgnostician access to internal registers in the control processor system, access to a dedicated read only storage for servicing, and logical interface to the main control processor for the purpose of entering instructions and directing functional operations to test each component of the system.

Claims

1. Data communications controller apparatus for concentrating messages destined to or from a plurality of relatively lower speed users'"'"' communications ports from or to a lesser plurality of relatively higher speed communications ports, comprising:

a plurality of communications ports; and

a plurality of communications ports interface adapters, each said adapter being connectable with a said port;

means for connecting each said port to a said adapter;

each said adapter comprising a microprocessor for handling communications to or from a port in the port format and protocol and for initiating and controlling direct memory accesses to main memory of another processor;

a control unit;

said control unit comprising a microprocessor, main memory and a direct memory access input/output interface for handling communications between said adapters and said main memory;

address and data busses respectively interconnecting said adapters, said control unit and said main memory for communication therebetween; and

said main memory being accessible through said busses via direct memory accesses initiated and controlled by said adapters utilizing said DMA interface.

2. Apparatus as described in claim 1, further comprising:

an arbitration and control means connected to said control unit, to said adapters, and to said data bus for arbitrating among and sequentially granting access to individual, simultaneously presented requests for access to said bus and for arbitrating among and sequentially granting to simultaneously presented requests for interrupts to said control unit.

3. Apparatus as described in claim 2, further comprising:

a memory mapped input/output interface means connected to said address bus for associating addresses presented thereto with specific locations of registers or controls for said adapters to which data may be sent or from which it may be received.

4. Apparatus as described in claim 3, further comprising:

means for programming said adapter'"'"'s microprocessors for the specific user port format and protocol requirements to which each adapter must respond; and

means in each said adapter for formatting and deformatting data at said user interface into or out of the specific port protocol and for presenting pure data to or receiving pure data from said main memory via DMA requests controlled by said microprocessors.

5. Apparatus as described in claim 4, further comprising:

a service interface means connected to one of said adapters and including a service address bus, a service data bus and a dedicated readable only memory and a machine status register and a machine check register;

said busses connecting said service interface to said memory and to said registers, said registers being connected via the said address and data busses connected to said control unit to only receive input therefrom and being connected to said service address and service data busses to only be read by said adapter connected to said service interface.

6. Apparatus as described in claim 2, further comprising:

a service interface means connected to one of said adapters and including a service address bus, a service data bus and a dedicated readable only memory and a machine status register and a machine check register;

said busses connecting said service interface to said memory and to said registers, said registers being connected via the said address and service data busses connected to said control unit to only receive input therefrom and being connected to said service address and service data busses to only be read by said adapter connected to said service interface.

7. Apparatus as described in claim 2 and further comprising:

a diagnostic service means including an address comparison register, a data comparison register and a function indicator register, comparison logic and an interrupt signalling means, a memory mapped I/O decoder for loading said registers, all of which being connected to said address and data busses and being connected to said control unit to be written by said control unit.

8. Apparatus as described in claim 3, further comprising:

a service interface means connected to one of said adapters and including a service address bus, a service data bus and a dedicated readable only memory and a machine status register and a machine check register;

said busses connecting said service interface to said memory and to said registers, said registers being connected via the said address and service data busses connected to said control unit to only receive input therefrom and being connected to said service address and service data busses to only be read by said adapter connected to said service interface.

9. Apparatus as described in claim 3 and further comprising:

a diagnostic service means including an address comparison register, a data comparison register and a function indicator register, comparison logic and an interrupt signalling means, a memory mapped I/O decoder for loading said registers, all of which being connected to said address and data busses and being connected to said control unit to be written by said control unit.

10. Apparatus as described in claim 4 and further comprising:

a diagnostic service means including an address comparison register, a data comparison register and a function indicator register, comparison logic and an interrupt signalling means, a memory mapped I/O decoder for loading said registers, all of which being connected to said address and data busses and being connected to said control unit to be written by said control unit.

11. Apparatus as described in claim 1, further comprising:

a service interface means connected to one of said adapters and including a service address bus, a service data bus and a dedicated readable only memory and a machine status register and a machine check register;

said busses connecting said service interface to said memory and to said registers, said registers being connected via the said address and service data busses connected to said control unit to only receive input therefrom and being connected to said service address and service data busses to only be read by said adapter connected to said service interface.

12. Apparatus as described in claim 11 and further comprising:

a diagnostic service means including an address comparison register, a data comparison register and a function indicator register, comparison logic and an interrupt signalling means, a memory mapped I/O decoder for loading said registers, all of which being connected to said address and data busses and being connected to said control unit to be written by said control unit and read via said service busses to aid in diagnosis of errors.