Manufacturing line control system

• US 4,870,590 A
• Filed: 01/22/1988
• Issued: 09/26/1989
• Est. Priority Date: 01/30/1987
• Status: Expired due to Fees

• Current Assignee: Yokogawa Electric Corporation
• Original Assignee: Yokogawa Electric Corporation
• Inventors: Kanno, Fujio, Kawata, Yasunori
• Primary Examiner(s): RUGGIERO, JOSEPH F
• Application Number:
  US07/146,941
• Time in Patent Office: 613 Days
• Field of Search: 364/132, 364/148, 364/468, 364/513, 364/200, 364/900, 364/300, 364/474.11, 364/131, 364/478, 364/138, 901/9, 901/44, 901/47, 901/7, 318/568
• US Class Current: 700/115
• CPC Class Codes: G05B 19/41835 characterised by programme execution
• CPC Class Codes: G05B 2219/33167 Bus arbitration, switch computer to different memory
• CPC Class Codes: G05B 2219/35548 1-to-16-bit conversion
• CPC Class Codes: G05B 2219/36371 Barcode reader
• CPC Class Codes: G06F 13/1631 through address comparison
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A manufacturing line control system wherein the hardware region of a main memory is divided on basis of different pieces of information to be stored, the main memory being in a CPU board within a line computer which synthetically judges and processes data transmitted from a manufacturing line; and access control portions are disposed on each of the regions for performing high speed access upon instruction of identical page by a microprocessor. Various analog signal, digital signal and status signal issued from a product passing through the manufacturing line are inputted from the line computer into various equipment installed on the manufacturing line, and control signals are transmitted to the various equipment by a line controller including an input-output portion with which a plurality of card equipment is detachably provided for the application of various types of manufacturing line. The system achieves automation at the manufacturing line site, reduces power consumption, stabilizes manufacturing at high quality, enables efficient small scale manufacture of many different types of products and enhances operability.

Claims

1. In a manufacturing line control system comprising a line controller which performs various processing to products passing through a manufacturing line, and a line computer which conducts data processing from the line controller and send instructions thereto, the improvement comprising

said line controller comprising an input portion which receives signals indicative of information as to said products passing through said manufacturing line and transmitted from various equipment installed on said manufacturing line;

an output portion which supplies control signals to said various equipment; and

a transmission interface for communicating with one of a host line computer and other line controllers; and

said line computer comprising a microprocessor;

a first bus connected to said microprocessor;

a main memory consisting of a DRAM, a SRAM and a EPROM, said main memory being connected to said first bus and subjected to access by said microprocessor;

a second bus whose bit number is smaller than that of said first bus;

a bit number converting interface for controlling operation timing and connected between said first and second buses;

a keyboard connected to said second bus through an interface;

a back plane bus connected to said second bus through a bus interface;

a CRT display device;

a display control means connected to said back plane bus for controlling said CRT display device; and

a bus interface connected to said back plane bus and performing transmission relative to said line controller.

2. The system of claim 1, wherein said EPROM has stored therein a start edge program;

wherein said microprocessor has a stack segment indexed to said SRAM; and

said microprocessor has a program segment and a data segment indexed to said DRAM.

3. The system of claim 1, wherein said first bus comprises a 32 bit type bus;

and said second bus comprises a 16 bit type bus.

4. The control system of claim 1, wherein said display control means comprises a graphic image control portion having a frame buffer for controlling graphic image;

a character image control portion having a character generator for controlling character image; and

a signal converting portion for performing parallel-serial conversion of a signal from one of said graphic image control portion and said character image control portion.

5. The system of claim 1, wherein said line computer comprises a bus arbiter for determining a bus master occupying therein one of said first and second bus;

and a priority register for reading out and writing from a plurality of bus masters connected to one of said first and second buses.

6. The system of claim 1, wherein said line controller comprises an internal bus and an ordinary input-output portion adapted to input and output one of analog signals and digital signals relative to said various equipment.

7. The system of claim 1, wherein said line controller comprises a sequence input-output portion for receiving a sequence element disposed on said manufacturing line and a signal;

and a sequence control portion for receiving a signal from said sequence input-output portions and for performing sequence control according to a sequence table defining a processing order of sequence control.

8. The system of claim 6, wherein said ordinary input-output portion comprises a local input-output card which comprises an interface for receiving a signal from a transmission line;

a signal converting portion for converting input signals to CRT display signals; and

a microprocessor for controlling transmission relative to the display control means and said internal bus of said line controller.

9. The system of claim 6, wherein said ordinary input-output portion comprises a GP-IB input-output card which comprises a connector connected to a GP-IB transmission line;

GP-IB control portion; and

a microprocessor for communicating signals relative to said GP-IB control portion and for controlling communication with said internal bus of said line controller.

10. The system of claim 6, wherein said ordinary input-output portion comprises an input multiplexer for selecting and receiving several analog voltage signal from an industrial signal converter;

a digital signal converting portion for converting inputted voltage to a digital signal;

an output portion for outputting the digital signal into said internal bus of said line controller;

an analog signal converting portion for converting control signals provided from said internal bus of said line controller to analog signals; and

an output multiplexer for outputting said analog signals to a predetermined point.

11. The system of claim 6, wherein said ordinary input-output portion comprises a pulse counter for receiving several pulse row from an industrial signal converter;

a data selector for selecting several points of pulse counter; and

a bus interface in said line controller.

12. The system of claim 6, wherein said ordinary input-output portion comprises a status input-output card, said status input-output card comprising a status input portion for receiving several points of status signals from an industrial signal relay unit;

a selecting portion for selecting several points of said status input portion;

an output portion for outputting obtained status signal to said internal bus of said line controller; and

a status output portion for outputting the status signal supplied from said internal bus of said line controller to a corresponding outputting point.

13. The system of claim 7, wherein said sequence input-output portion comprises a sequence input card, said sequence input card comprising an input portion for receiving a plurality of external voltage signals;

a photo-coupler electrically insulated from outside for converting the voltage signals into ON-OFF signals; and

a signal transmitting portion for transmitting signals from said photo-coupler to said internal bus of said line controller.

14. The system of claim 7, wherein said sequence input-output portion comprises a sequence output portion which comprises an input buffer for holding the status signal from said internal bus of said line controller;

and an output portion for outputting ON-OFF signals to an instructed point, said ON-OFF signals corresponding to the signals held in said input buffer.

15. In a manufacturing line control system comprising a line controller which performs various processing to products passing through a manufacturing line, and a line computer which conducts data processing from said line controller and send instructions thereto, the improvement comprising

said line controller comprising an input portion which receives signals indicative of information as to said products passing through said manufacturing line and transmitted from various equipment installed in said manufacturing line;

an output portion which supplies control signals to said various equipment; and

a transmission interface for communicating with one of a host line computer and other line controllers; and

said line computer comprising a microprocessor;

a main memory which is subjected to access by said microprocessor;

a CRT display device;

a display control means for controlling said CRT display device; and

a keyboard input means;

wherein

said main memory comprises an EPROM including starting edge program;

a SRAM for stack segment of the microprocessor; and

a DRAM in which stored information is subjected to page control, said DRAM being physically allotted with a data segment and a program segment, said data segment storing therein an intermediary language as a machine language routine with respect to a plurality of basic user task program inputted externally, and said program segment storing therein a machine language and a basic interpreter functioning portion to which the microprocessor refers; and

wherein

said line computer further comprising an access control portion, said access control portion comprising a page memory means for holding page information which is previously subjected to access in the data segment and the program segment through the microprocessor;

a comparator for comparing row address given by a present cycle from said microprocessor with said page information; and

a DRAM controller for performing access by a column address when a coincident signal is outputted from said comparator, and for controlling page change when a non-coincident signal is outputted from said comparator.

16. The system of claim 15, wherein said DRAM controller comprises means for issuing signals to start refreshing operation, and for restarting access in accordance with page information held in said page memory means upon termination of said refreshing operation.