Comprehensive logic circuit layout system

• US 4,870,598 A
• Filed: 08/04/1987
• Issued: 09/26/1989
• Est. Priority Date: 08/04/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kalyan, Vibhu, Bosshart, Patrick, Houston, Theodore, Shaw, Ching-Hao, Matzke, Douglas
• Primary Examiner(s): Arnold, Bruce Y.
• Assistant Examiner(s): Callaghan, Terry S.
• Application Number:
  US07/081,419
• Time in Patent Office: 784 Days
• Field of Search: 364/490, 364/491, 364/488, 364/489, 364/480
• US Class Current: 716/116
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and one of the column locations. Elongate gate conductors (e.g., G, H, I) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). A plurality of elongate second conductors (222) connect to selected ones of the sources or drains of the transistors (224) and to non-Boolean portions of the dynamic logic circuits. The non-Boolean portions are formed in an adjacent tile section (214) in the semi-conductor layer separate from the logic array (212). w

Claims

1. A method for laying out a plurality of logic circuits on a face of a semiconductor layer, comprising the steps of:

mapping a Boolean portion of each logic circuit into a logic array on the face, in a left to right order, having a plurality of rows and columns, said Boolean portion including at least one logic gate transistor formed at an intersection of one of said rows and one of said columns and optimizing the order of the Boolean portions inside the array for dimensional compactness of the array, said optimizing the order of the Boolean portions including assigning a row order to each of a plurality of input signals used in the Boolean portions, assigning an initial columnar order to each of the Boolean portions, calculating a cost function for the present columnar order based on criteria including matrix compactness, reordering the Boolean portions in a new columnar order, recalculating the cost function, adopting the new columnar order as the present columnar order if its cost function has a better value, repeating the steps of reordering, recalculating and adopting until a satisfactory cost function value is achieved, forming a virtual gate conductor for each input signal and biasing one of the criteria on the lengths of the gate conductors;

implementing a non-Boolean portion of each logic circuit in a tile;

forming the tile in a tile section on the face near the logic array;

coupling the non-Boolean portion of each logic circuit with the Boolean portion thereof;

originating at least one logic equation of a dynamic domino-type; and

forming a precharge clock and a sense amplifier in a tile for the dynamic domino-type logic equation.

2. The method of claim 1, wherein the dynamic domino-type equation is a dynamic latch logic equation, the method further including the step of forming a latch in the tile for the dynamic latch logic equation.