DRAM controller cache

• US 4,870,622 A
• Filed: 06/24/1988
• Issued: 09/26/1989
• Est. Priority Date: 06/24/1988
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lee, Sherman, Aria, Percy R.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/211,511
• Time in Patent Office: 459 Days
• Field of Search: 365/189, 365/230, 365/233, 365/230.02, 365/230.03, 365/238.5, 365/193
• US Class Current: 365/230.02
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns. First data is accessed at a predetermined column and row location. The predetermined row location of the first data is then recorded. The location of second data is then recorded. Then the locations of the first and second data are compared. A row compare signal is generated if the row value of both first and second data are identical. Only the column address is varied in response to the row compare signal.

Claims

1. A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns, the steps comprising:

(a) accessing first data at a predetermined column and row location;

(b) recording said predetermined row location of said first data;

(c) recording the row location of second data;

(d) comparing row locations of said first and said second data;

(e) generating a row compare signal and maintaining a row address strobe in a charged state to eliminate the necessity for strobe precharging when accessing said second data if said row locations of both first and second data are identical; and

(f) varying only said column address to said memory in response to said row compare signal, said varying step initiating access of said second data.

2. The method in accordance with claim 1, further comprising the steps of:

(g) updating a storage register with the address of said second data when said comparison of locations of said first and second data is not identical.

3. The method in accordance with claim 1, wherein during said step of accessing first data, a row address strobe signal is enabled.

4. The method in accordance with claim 3, wherein during said step of varying only said column address, said row address strobe signal is maintained.

5. The method in accordance with claim 4, wherein said row address strobe signal is maintained by a timing generator.

6. The method in accordance with claim 4, wherein said row address strobe signal is disabled when said comparison of row locations of said first and second data is not identical.

13. The method in accordance with claim 1 wherein said memory is a DRAM.

14. The method in accordance with claim 13 wherein said DRAM is a page mode DRAM.

15. The method in accordance with claim 13 wherein said DRAM is a fast page mode DRAM.

16. The method in accordance with claim 13 wherein said DRAM is a nibble mode DRAM.

7. A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same bank and row but in different columns, the steps comprising:

(a) accessing first data at a predetermined bank, column and row location;

(b) recording said predetermined bank and row locations of said first data;

(c) recording the bank and row locations of second data;

(d) comparing bank and row locations of said first and said second data;

(e) generating a compare signal and maintaining a row address strobe in a charged state to eliminate the necessity for strobe precharging when addressing said second data if said bank and said row values of both said first and second data are identical; and

(f) varying only said column address to said memory in response to said compare signal, said varying step initiating access of said second data.

8. The method in accordance with claim 7, further comprising the step of:

(g) updating a storage register with the address of said second data when said comparison of location of said first and second data is not identical.

9. The method in accordance with claim 7, wherein during said step of accessing first data, a row address strobe signal is enabled.

10. The method in accordance with claim 9, wherein during said step of varying only said column address, said row address strobe signal is maintained.

11. The method in accordance with claim 10, wherein said row address strobe signal is maintained by a timing generator.

12. The method in accordance with claim 10, wherein said row address strobe signal is disabled when said comparison of locations of said first and second data is not identical.

17. The method in accordance with claim 7 wherein said memory is a DRAM.

18. The method in accordance with claim 17 wherein said DRAM is a page mode DRAM.

19. The method in accordance with claim 17 wherein said DRAM is a fast page mode DRAM.

20. The method in accordance with claim 17 wherein said DRAM is a nibble mode DRAM.