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DRAM controller cache

  • US 4,870,622 A
  • Filed: 06/24/1988
  • Issued: 09/26/1989
  • Est. Priority Date: 06/24/1988
  • Status: Expired due to Term
First Claim
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1. A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns, the steps comprising:

  • (a) accessing first data at a predetermined column and row location;

    (b) recording said predetermined row location of said first data;

    (c) recording the row location of second data;

    (d) comparing row locations of said first and said second data;

    (e) generating a row compare signal and maintaining a row address strobe in a charged state to eliminate the necessity for strobe precharging when accessing said second data if said row locations of both first and second data are identical; and

    (f) varying only said column address to said memory in response to said row compare signal, said varying step initiating access of said second data.

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