FSK demodulation circuit

• US 4,870,659 A
• Filed: 08/29/1988
• Issued: 09/26/1989
• Est. Priority Date: 08/29/1987
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Takeda, Yukio, Nakamura, Takaharu, Watanabe, Yasunobu, Takano, Takeshi, Oishi, Yasuyuki
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US07/237,535
• Time in Patent Office: 393 Days
• Field of Search: 375/45, 375/88, 375/94, 375/82, 455/205, 455/334, 455/337, 329/110, 329/126, 329/105, 329/124, 329/104
• US Class Current: 375/328
• CPC Class Codes: H04L 27/1525 using quadrature demodulation

Abstract

An FSK demodulation circuit which receives as input an FSK modulated reception signal, obtains two quadrature pulse trains, i.e., a first pulse train and a second pulse train, from a phase detection circuit, is provided with at least two sampling means which use the edge of one of the pulse trains and sample the logic of the other pulse train, produces two or more sample outputs at different timings, and determines the logic of the reproduced data from a combination of the logics "1" and "0" of the sample outputs.

Claims

1. A frequency shift keying (FSK) demodulation circuit having:

phase detection means which receives as an input an FSK modulated reception signal and performs phase detection on the same so as to produce quadrature I-ch and Q-ch analog base band signals and which further converts said analog base band signals to digital signals and outputs a first pulse train and a second pulse train, respectively, and

data reproducing means which reproduces the original data from the first pulse train and the second pulse train to output reproduced data,

said data reproducing means comprising;

first sampling means which uses an edge of the second pulse train and samples the logic of the first pulse train to obtain a first sample output;

second sampling means which uses an edge of the first pulse train and samples the inverted logic of the second pulse train to obtain a second sample output, said first and second sampling means using the edges of the second and first pulse trains, respectively, for sampling the logics at mutually different timings;

decision means which receives as inputs the sample outputs from said first and second sampling means and determines the logic of said reproduced data by a predetermined decision operation on the sample outputs, said decision means including a coincidence detection part which detects coincidence or noncoincidence of the logic levels of said first and second sample outputs and a latch circuit which forms the logic level of said reproduced data using the current logic level upon coincidence and forms the logic level of said reproduced data with the logic level just before, held internally, upon noncoincidence; and

delay means for applying a predetermined delay to said first sample output and applying the delayed first sample output to said latch circuit, said delay means providing a delay time set substantially equal to the time required for detection of coincidence at said coincidence detection part.

2. An FSK demodulation circuit according to claim 1, wherein said first and second sampling means are comprised of first and second D-type flip-flops receiving as D inputs said first and second pulse trains, respectively, and as clock inputs the second and first pulse trains, respectively, and wherein said first and second sample outputs are obtained from a Q output and a Q output of said first and second D-type flip-flops, respectively.

3. An FSK demodulation circuit according to claim 1, wherein said coincidence detection part is comprised of an EXOR gate receiving as inputs said first and second sample outputs and an inverter connected to the output of the EXOR gate and, upon coincidence of the first and second sample outputs, outputs logic "1" from said inverter and upon noncoincidence of the first and second sample outputs, outputs logic "0", and controls said latch circuit.

4. A frequency shift keying (FSK) demodulation circuit having:

phase detection means which receives as an input an FSK modulated reception signal and performs phase detection on the FSK modulated reception signal so as to produce quadrature I-ch and Q-ch analog base band signals and which further converts said analog base band signals to respective digital signals and outputs a first pulse train and a second pulse train, respectively; and

data reproducing means which reproduces the original data from the first pulse train and the second pulse train and outputs a reproduced data,

said data reproducing means comprising;

first sampling means which uses the leading edge of the second pulse train and samples the logic of the first pulse train to obtain a first sample output;

second sampling means which uses the trailing edge of the second pulse train and samples the inverted logic of the first pulse train to obtain a second sample output;

means for inverting the second pulse train prior to its use by said second sampling means;

decision means which receives as input the sample outputs from said first and second sampling means and determines the logic of said reproduced data by a predetermined decision operation on the sample outputs, said decision means including a coincidence detection part which detects coincidence or noncoincidence of the logics of said first and second sample outputs and a latch part which forms the logic of said reproduced data using the current logic level upon coincidence and forms the logic of said reproduced data with the logic level just before, held internally, upon noncoincidence.

5. An FSK demodulation circuit according to claim 4, wherein said data reproducing means further comprises delay means for applying a predetermined delay to said sample first output and applying the same to said latch part, said delay means providing a delay time set substantially equal to the time required for detection of coincidence at said coincidence detection part.

6. An FSK demodulation circuit according to claim 4, wherein said first sampling means is comprised of a first D-type flip-flop receiving as a D input and clock input said first and second pulse trains, respectively, and said second sampling means is comprised of a second D-type flip-flop receiving as a D input said first pulse train and as a clock input said inverted second pulse train, said first and second sample outputs being obtained from the Q output and the Q output of said first and second D-type flip-flops, respectively.

7. An FSK demodulation circuit according to claim 4, wherein said coincidence detection part is comprised of an EXOR gate receiving as inputs said first and second sample outputs and inverting means for inverting the output of the EXOR gate and, upon coincidence of the first and second sample outputs, outputs logic "1" from said inverting means and upon noncoincidence of the first and second sample outputs, outputs logic "0" and controls said latch part.

8. A frequency shift keying (FSK) demodulation circuit having:

phase detection means which receives as an input an FSK modulated reception signal and performs phase detection on the FSK modulated reception signal so as to produce quadrature I-ch and Q-ch analog base band signals and which further converts said analog base band signals to respective digital signals and outputs a first pulse train and a second pulse train, respectively; and

data reproducing means which reproduces the original data from the first pulse train and the second pulse train and outputs reproduced data,

said data reproducing means comprising;

first, second, third and fourth sampling means which use the leading edge and the trailing edge of the second pulse train and sample the logic or inverted logic of the first pulse train and use the leading edge and the trailing edge of the first pulse train and sample the logic or inverted logic of the second pulse train to obtain first, second, third and fourth sample outputs; and

decision means for determining the reproduced data, comprising majority logic decision means which makes a majority logic decision based on the sample outputs and outputs a decision result, and holding means which, when the decision result is of a majority of the logic level "1", transmits "1" as the logic of the reproduced data and, when the decision result is of a majority of the logic level "0", transmits "0".

9. An FSK demodulation circuit according to claim 8, wherein when the decision result is of the same number of logic levels "1" and "0", said holding means outputs the previously held logic as it is and uses it as the logic of the reproduced data.

10. An FSK demodulation circuit according to claim 9, wherein said decision means further comprises delay means provided between said majority logic decision means and said holding means, said delay means for giving a delay time to the decision result set substantially equal to the time required for said majority logic decision.

11. An FSK demodulation circuit according to claim 8, wherein said first sampling means is comprised of a first D-type flip-flop and receives as a D input and a clock input said first and second pulse trains, respectively, and said third sampling means is comprised of a third D-type flip-flop which receives as a D input and a clock input said first and second pulse trains, respectively, through first and second inverters, and

said second sampling means is comprised of a second D-type flip-flop and receives as a D input and a clock input said second and first pulse trains, respectively, and said fourth sampling means is comprised of a fourth D-type flip-flop which receives as a D input and a clock input said second and first pulse trains, respectively, through the second and first inverters.

12. An FSK demodulation circuit according to claim 8, wherein said majority logic decision means comprises a memory which receives as address inputs said sample outputs and a logic predetermined in accordance with combinations of logic levels "1" and "0" of said sample outputs is read out from said memory and transmitted to said holding means.

13. An FSK demodulation circuit according to claim 8, wherein said holding means is comprised of a latch circuit.

14. An FSK demodulation circuit according to claim 8, wherein said majority logic decision means is comprised of a logic gate.

15. an FSK demodulation circuit according to claim 8, wherein said majority logic decision means is comprised of an analog adder circuit.

16. A frequency shift keying (FSK) demodulation circuit having:

phase detection means which receives as an input an FSK modulated reception signal and performs phase detection on the FSK modulated receptions signal so as to produce quadrature I-ch and Q-ch analog base band signals and which further converts said analog base band signals to respective digital signals and outputs a first pulse train and a second pulse train, respectively; and

data reproducing means which reproduces the original data from the first pulse train and the second pulse train and outputs reproduced data,

said data reproducing means comprising;

first, second and third sampling means which use the leading edge and the trailing edge of the first and second pulse trains and sample the logic or inverted logic of the first and second pulse trains to obtain first, second and third sample outputs; and

decision means for determining the reproduced data, comprising majority logic decision means for making a majority logic decision based on the sample outputs and outputs a decision result, and holding means which, when said decision result is of a number of logic levels "1" greater than a number of logic levels "0", transmits "1" as the logic of the reproduced data and, when the number of logic levels "0" in said decision result is greater than the number of logic levels "1", transmits "0".

17. An FSK demodulation circuit according to claim 16, wherein said first sampling means is comprised of a first D-type flip-flop and receives as its clock input and D input the first and second pulse trains, respectively, said second sampling means is comprised of a second D-type flip-flop and receives as its clock input and D input the second and first pulse trains, respectively and said third sampling means is comprised of a third D-type flip-flop and receives as its D input the first pulse train and as its clock input the second pulse train which has passed through an inverter.

18. An FSK demodulation circuit according to claim 16, wherein said majority logic decision means is comprised of a memory which receives as address inputs said first, second and third sample outputs, and a logic predetermined in accordance with combinations of logic levels "1" and "0" of said sample outputs is read out from said memory and transmitted to said holding means.